cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,imx27-pinctrl.txt (3222B)

      1* Freescale IMX27 IOMUX Controller
      2
      3Required properties:
      4- compatible: "fsl,imx27-iomuxc"
      5
      6The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
      7
      8Required properties for pin configuration node:
      9- fsl,pins: three integers array, represents a group of pins mux and config
     10  setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
     11
     12  PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
     13  configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
     14  number on the specific port (between 0 and 31).
     15
     16  MUX_ID is
     17    function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
     18
     19      function value is used to select the pin function.
     20      Possible values:
     21          0 - Primary function
     22          1 - Alternate function
     23          2 - GPIO
     24      Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
     25
     26      direction defines the data direction of the pin.
     27      Possible values:
     28          0 - Input
     29          1 - Output
     30      Register: DDIR
     31
     32      gpio_oconf configures the gpio submodule output signal. This does not
     33      have any effect unless GPIO function is selected. A/B/C_IN are output
     34      signals of function blocks A,B and C. Specific function blocks are
     35      described in the reference manual.
     36      Possible values:
     37          0 - A_IN
     38          1 - B_IN
     39          2 - C_IN
     40          3 - Data Register
     41      Registers: OCR1, OCR2
     42
     43      gpio_iconfa/b configures the gpio submodule input to functionblocks A and
     44      B. GPIO function should be selected if this is configured.
     45      Possible values:
     46          0 - GPIO_IN
     47          1 - Interrupt Status Register
     48          2 - Pulldown
     49          3 - Pullup
     50      Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
     51
     52  CONFIG can be 0 or 1, meaning Pullup disable/enable.
     53
     54
     55The iomux controller has gpio child nodes which are embedded in the iomux
     56control registers. They have to be defined as child nodes of the iomux device
     57node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"
     58properties for the iomux device node are required.
     59
     60Example:
     61
     62iomuxc: iomuxc@10015000 {
     63	compatible = "fsl,imx27-iomuxc";
     64	reg = <0x10015000 0x600>;
     65	#address-cells = <1>;
     66	#size-cells = <1>;
     67	ranges;
     68
     69	gpio1: gpio@10015000 {
     70		...
     71	};
     72
     73	...
     74
     75	uart {
     76		pinctrl_uart1: uart-1 {
     77			fsl,pins = <
     78				0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
     79				0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
     80				0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
     81				0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
     82			>;
     83		};
     84
     85		...
     86	};
     87};
     88
     89
     90For convenience there are macros defined in imx27-pinfunc.h which provide PIN
     91and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
     92are defined in the i.MX27 reference manual.
     93
     94The above example using macros:
     95
     96iomuxc: iomuxc@10015000 {
     97	compatible = "fsl,imx27-iomuxc";
     98	reg = <0x10015000 0x600>;
     99	#address-cells = <1>;
    100	#size-cells = <1>;
    101	ranges;
    102
    103	gpio1: gpio@10015000 {
    104		...
    105	};
    106
    107	...
    108
    109	uart {
    110		pinctrl_uart1: uart-1 {
    111			fsl,pins = <
    112				MX27_PAD_UART1_TXD__UART1_TXD 0x0
    113				MX27_PAD_UART1_RXD__UART1_RXD 0x0
    114				MX27_PAD_UART1_CTS__UART1_CTS 0x0
    115				MX27_PAD_UART1_RTS__UART1_RTS 0x0
    116			>;
    117		};
    118
    119		...
    120	};
    121};