cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,imx6q-pinctrl.txt (1483B)


      1* Freescale IMX6Q IOMUX Controller
      2
      3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
      4and usage.
      5
      6Required properties:
      7- compatible: "fsl,imx6q-iomuxc"
      8- fsl,pins: two integers array, represents a group of pins mux and config
      9  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
     10  pin working on a specific function, CONFIG is the pad setting value like
     11  pull-up for this pin. Please refer to imx6q datasheet for the valid pad
     12  config settings.
     13
     14CONFIG bits definition:
     15PAD_CTL_HYS                     (1 << 16)
     16PAD_CTL_PUS_100K_DOWN           (0 << 14)
     17PAD_CTL_PUS_47K_UP              (1 << 14)
     18PAD_CTL_PUS_100K_UP             (2 << 14)
     19PAD_CTL_PUS_22K_UP              (3 << 14)
     20PAD_CTL_PUE                     (1 << 13)
     21PAD_CTL_PKE                     (1 << 12)
     22PAD_CTL_ODE                     (1 << 11)
     23PAD_CTL_SPEED_LOW               (1 << 6)
     24PAD_CTL_SPEED_MED               (2 << 6)
     25PAD_CTL_SPEED_HIGH              (3 << 6)
     26PAD_CTL_DSE_DISABLE             (0 << 3)
     27PAD_CTL_DSE_240ohm              (1 << 3)
     28PAD_CTL_DSE_120ohm              (2 << 3)
     29PAD_CTL_DSE_80ohm               (3 << 3)
     30PAD_CTL_DSE_60ohm               (4 << 3)
     31PAD_CTL_DSE_48ohm               (5 << 3)
     32PAD_CTL_DSE_40ohm               (6 << 3)
     33PAD_CTL_DSE_34ohm               (7 << 3)
     34PAD_CTL_SRE_FAST                (1 << 0)
     35PAD_CTL_SRE_SLOW                (0 << 0)
     36
     37Refer to imx6q-pinfunc.h in device tree source folder for all available
     38imx6q PIN_FUNC_ID.