cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,imx6ul-pinctrl.txt (1630B)


      1* Freescale i.MX6 UltraLite IOMUX Controller
      2
      3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
      4and usage.
      5
      6Required properties:
      7- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
      8  "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
      9- fsl,pins: each entry consists of 6 integers and represents the mux and config
     10  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val
     11  input_val> are specified using a PIN_FUNC_ID macro, which can be found in
     12  imx6ul-pinfunc.h under device tree source folder.  The last integer CONFIG is
     13  the pad setting value like pull-up on this pin.  Please refer to i.MX6 UltraLite
     14  Reference Manual for detailed CONFIG settings.
     15
     16CONFIG bits definition:
     17PAD_CTL_HYS                     (1 << 16)
     18PAD_CTL_PUS_100K_DOWN           (0 << 14)
     19PAD_CTL_PUS_47K_UP              (1 << 14)
     20PAD_CTL_PUS_100K_UP             (2 << 14)
     21PAD_CTL_PUS_22K_UP              (3 << 14)
     22PAD_CTL_PUE                     (1 << 13)
     23PAD_CTL_PKE                     (1 << 12)
     24PAD_CTL_ODE                     (1 << 11)
     25PAD_CTL_SPEED_LOW               (0 << 6)
     26PAD_CTL_SPEED_MED               (1 << 6)
     27PAD_CTL_SPEED_HIGH              (3 << 6)
     28PAD_CTL_DSE_DISABLE             (0 << 3)
     29PAD_CTL_DSE_260ohm              (1 << 3)
     30PAD_CTL_DSE_130ohm              (2 << 3)
     31PAD_CTL_DSE_87ohm               (3 << 3)
     32PAD_CTL_DSE_65ohm               (4 << 3)
     33PAD_CTL_DSE_52ohm               (5 << 3)
     34PAD_CTL_DSE_43ohm               (6 << 3)
     35PAD_CTL_DSE_37ohm               (7 << 3)
     36PAD_CTL_SRE_FAST                (1 << 0)
     37PAD_CTL_SRE_SLOW                (0 << 0)