cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel,pinctrl-thunderbay.yaml (2862B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-thunderbay.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Intel Thunder Bay pin controller Device Tree Bindings
      8
      9maintainers:
     10  - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
     11
     12description: |
     13  Intel Thunder Bay SoC integrates a pin controller which enables control
     14  of pin directions, input/output values and configuration
     15  for a total of 67 pins.
     16
     17properties:
     18  compatible:
     19    const: intel,thunderbay-pinctrl
     20
     21  reg:
     22    maxItems: 1
     23
     24  gpio-controller: true
     25
     26  '#gpio-cells':
     27    const: 2
     28
     29  gpio-ranges:
     30    maxItems: 1
     31
     32  interrupts:
     33    description:
     34      Specifies the interrupt lines to be used by the controller.
     35    maxItems: 2
     36
     37  interrupt-controller: true
     38
     39  '#interrupt-cells':
     40    const: 2
     41
     42patternProperties:
     43  '^gpio@[0-9a-f]*$':
     44    type: object
     45
     46    description:
     47      Child nodes can be specified to contain pin configuration information,
     48      which can then be utilized by pinctrl client devices.
     49      The following properties are supported.
     50
     51    properties:
     52      pins:
     53        description: |
     54          The name(s) of the pins to be configured in the child node.
     55          Supported pin names are "GPIO0" up to "GPIO66".
     56
     57      bias-disable: true
     58
     59      bias-pull-down: true
     60
     61      bias-pull-up: true
     62
     63      drive-strength:
     64        description: Drive strength for the pad.
     65        enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
     66
     67      bias-bus-hold:
     68        type: boolean
     69
     70      input-schmitt-enable:
     71        type: boolean
     72
     73      slew-rate:
     74        description: GPIO slew rate control.
     75                      0 - Slow
     76                      1 - Fast
     77        enum: [0, 1]
     78
     79additionalProperties: false
     80
     81required:
     82  - compatible
     83  - reg
     84  - gpio-controller
     85  - '#gpio-cells'
     86  - gpio-ranges
     87  - interrupts
     88  - interrupt-controller
     89  - '#interrupt-cells'
     90
     91examples:
     92  - |
     93    #include <dt-bindings/interrupt-controller/arm-gic.h>
     94    #include <dt-bindings/interrupt-controller/irq.h>
     95    // Example 1
     96    pinctrl0: gpio@0 {
     97        compatible = "intel,thunderbay-pinctrl";
     98        reg = <0x600b0000 0x88>;
     99        gpio-controller;
    100        #gpio-cells = <0x2>;
    101        gpio-ranges = <&pinctrl0 0 0 67>;
    102        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
    103                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
    104        interrupt-controller;
    105        #interrupt-cells = <2>;
    106    };
    107
    108    // Example 2
    109    pinctrl1: gpio@1 {
    110        compatible = "intel,thunderbay-pinctrl";
    111        reg = <0x600c0000 0x88>;
    112        gpio-controller;
    113        #gpio-cells = <0x2>;
    114        gpio-ranges = <&pinctrl1 0 0 53>;
    115        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
    116                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
    117        interrupt-controller;
    118        #interrupt-cells = <2>;
    119    };