mediatek,mt6797-pinctrl.yaml (5229B)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6797-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT6797 Pin Controller Device Tree Bindings 8 9maintainers: 10 - Sean Wang <sean.wang@kernel.org> 11 12description: |+ 13 The MediaTek's MT6797 Pin controller is used to control SoC pins. 14 15properties: 16 compatible: 17 const: mediatek,mt6797-pinctrl 18 19 reg: 20 minItems: 5 21 maxItems: 5 22 23 reg-names: 24 items: 25 - const: gpio 26 - const: iocfgl 27 - const: iocfgb 28 - const: iocfgr 29 - const: iocfgt 30 31 gpio-controller: true 32 33 "#gpio-cells": 34 const: 2 35 description: | 36 Number of cells in GPIO specifier. Since the generic GPIO 37 binding is used, the amount of cells must be specified as 2. See the below 38 mentioned gpio binding representation for description of particular cells. 39 40 interrupt-controller: true 41 42 interrupts: 43 maxItems: 1 44 45 "#interrupt-cells": 46 const: 2 47 48allOf: 49 - $ref: "pinctrl.yaml#" 50 51required: 52 - compatible 53 - reg 54 - reg-names 55 - gpio-controller 56 - "#gpio-cells" 57 58patternProperties: 59 '-[0-9]+$': 60 type: object 61 additionalProperties: false 62 patternProperties: 63 'pins': 64 type: object 65 additionalProperties: false 66 description: | 67 A pinctrl node should contain at least one subnodes representing the 68 pinctrl groups available on the machine. Each subnode will list the 69 pins it needs, and how they should be configured, with regard to muxer 70 configuration, pullups, drive strength, input enable/disable and input 71 schmitt. 72 $ref: "/schemas/pinctrl/pincfg-node.yaml" 73 74 properties: 75 pinmux: 76 description: 77 integer array, represents gpio pin number and mux setting. 78 Supported pin number and mux varies for different SoCs, and are 79 defined as macros in <soc>-pinfunc.h directly. 80 81 bias-disable: true 82 83 bias-pull-up: true 84 85 bias-pull-down: true 86 87 input-enable: true 88 89 input-disable: true 90 91 output-enable: true 92 93 output-low: true 94 95 output-high: true 96 97 input-schmitt-enable: true 98 99 input-schmitt-disable: true 100 101 drive-strength: 102 enum: [2, 4, 8, 12, 16] 103 104 slew-rate: 105 enum: [0, 1] 106 107 mediatek,pull-up-adv: 108 description: | 109 Pull up setings for 2 pull resistors, R0 and R1. User can 110 configure those special pins. Valid arguments are described as below: 111 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 112 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 113 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 114 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 115 $ref: /schemas/types.yaml#/definitions/uint32 116 enum: [0, 1, 2, 3] 117 118 mediatek,pull-down-adv: 119 description: | 120 Pull down settings for 2 pull resistors, R0 and R1. User can 121 configure those special pins. Valid arguments are described as below: 122 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 123 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 124 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 125 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 126 $ref: /schemas/types.yaml#/definitions/uint32 127 enum: [0, 1, 2, 3] 128 129 mediatek,tdsel: 130 description: | 131 An integer describing the steps for output level shifter duty 132 cycle when asserted (high pulse width adjustment). Valid arguments 133 are from 0 to 15. 134 $ref: /schemas/types.yaml#/definitions/uint32 135 136 mediatek,rdsel: 137 description: | 138 An integer describing the steps for input level shifter duty cycle 139 when asserted (high pulse width adjustment). Valid arguments are 140 from 0 to 63. 141 $ref: /schemas/types.yaml#/definitions/uint32 142 143 required: 144 - pinmux 145 146additionalProperties: false 147 148examples: 149 - | 150 #include <dt-bindings/interrupt-controller/irq.h> 151 #include <dt-bindings/interrupt-controller/arm-gic.h> 152 #include <dt-bindings/pinctrl/mt6797-pinfunc.h> 153 154 soc { 155 #address-cells = <2>; 156 #size-cells = <2>; 157 158 pio: pinctrl@10005000 { 159 compatible = "mediatek,mt6797-pinctrl"; 160 reg = <0 0x10005000 0 0x1000>, 161 <0 0x10002000 0 0x400>, 162 <0 0x10002400 0 0x400>, 163 <0 0x10002800 0 0x400>, 164 <0 0x10002C00 0 0x400>; 165 reg-names = "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt"; 166 gpio-controller; 167 #gpio-cells = <2>; 168 169 uart_pins_a: uart-0 { 170 pins1 { 171 pinmux = <MT6797_GPIO232__FUNC_URXD1>, 172 <MT6797_GPIO233__FUNC_UTXD1>; 173 }; 174 }; 175 }; 176 };