cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pinctrl-mcp23s08.txt (5994B)


      1Microchip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for
      28-/16-bit I/O expander with serial interface (I2C/SPI)
      3
      4Required properties:
      5- compatible : Should be
      6    - "mcp,mcp23s08" (DEPRECATED) for  8 GPIO SPI version
      7    - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
      8    - "mcp,mcp23008" (DEPRECATED) for  8 GPIO I2C version or
      9    - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
     10
     11    - "microchip,mcp23s08" for  8 GPIO SPI version
     12    - "microchip,mcp23s17" for 16 GPIO SPI version
     13    - "microchip,mcp23s18" for 16 GPIO SPI version
     14    - "microchip,mcp23008" for  8 GPIO I2C version or
     15    - "microchip,mcp23017" for 16 GPIO I2C version of the chip
     16    - "microchip,mcp23018" for 16 GPIO I2C version
     17    NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
     18    removed.
     19- #gpio-cells : Should be two.
     20  - first cell is the pin number
     21  - second cell is used to specify flags as described in
     22    'Documentation/devicetree/bindings/gpio/gpio.txt'. Allowed values defined by
     23    'include/dt-bindings/gpio/gpio.h' (e.g. GPIO_ACTIVE_LOW).
     24- gpio-controller : Marks the device node as a GPIO controller.
     25- reg : For an address on its bus. I2C uses this a the I2C address of the chip.
     26        SPI uses this to specify the chipselect line which the chip is
     27        connected to. The driver and the SPI variant of the chip support
     28        multiple chips on the same chipselect. Have a look at
     29        microchip,spi-present-mask below.
     30
     31Required device specific properties (only for SPI chips):
     32- mcp,spi-present-mask (DEPRECATED)
     33- microchip,spi-present-mask : This is a present flag, that makes only sense for SPI
     34        chips - as the name suggests. Multiple SPI chips can share the same
     35        SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a
     36        chip connected with the corresponding spi address set. For example if
     37        you have a chip with address 3 connected, you have to set bit3 to 1,
     38        which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not
     39        possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at
     40        least one bit to 1 for SPI chips.
     41    NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
     42    removed.
     43- spi-max-frequency = The maximum frequency this chip is able to handle
     44
     45Optional properties:
     46- #interrupt-cells : Should be two.
     47  - first cell is the pin number
     48  - second cell is used to specify flags.
     49- interrupt-controller: Marks the device node as a interrupt controller.
     50- drive-open-drain: Sets the ODR flag in the IOCON register. This configures
     51        the IRQ output as open drain active low.
     52- reset-gpios: Corresponds to the active-low RESET# pin for the chip
     53
     54Optional device specific properties:
     55- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices
     56        with two interrupt outputs (these are the devices ending with 17 and
     57        those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and
     58        IO 8-15 are bank 2. These chips have two different interrupt outputs:
     59        One for bank 1 and another for bank 2. If irq-mirror is set, both
     60        interrupts are generated regardless of the bank that an input change
     61        occurred on. If it is not set, the interrupt are only generated for the
     62        bank they belong to.
     63        On devices with only one interrupt output this property is useless.
     64- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This
     65        configures the IRQ output polarity as active high.
     66
     67Example I2C (with interrupt):
     68gpiom1: gpio@20 {
     69        compatible = "microchip,mcp23017";
     70        gpio-controller;
     71        #gpio-cells = <2>;
     72        reg = <0x20>;
     73
     74        interrupt-parent = <&gpio1>;
     75        interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
     76        interrupt-controller;
     77        #interrupt-cells=<2>;
     78        microchip,irq-mirror;
     79};
     80
     81Example SPI:
     82gpiom1: gpio@0 {
     83        compatible = "microchip,mcp23s17";
     84        gpio-controller;
     85        #gpio-cells = <2>;
     86        microchip,spi-present-mask = <0x01>;
     87        reg = <0>;
     88        spi-max-frequency = <1000000>;
     89};
     90
     91Pull-up configuration
     92=====================
     93
     94If pins are used as output, they can also be configured with pull-ups. This is
     95done with pinctrl.
     96
     97Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
     98for details of the common pinctrl bindings used by client devices,
     99including the meaning of the phrase "pin configuration node".
    100
    101Optional Pinmux properties:
    102--------------------------
    103Following properties are required if default setting of pins are required
    104at boot.
    105- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
    106- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
    107		<pinctrl-bindings.txt>.
    108
    109The pin configurations are defined as child of the pinctrl states node. Each
    110sub-node have following properties:
    111
    112Required properties:
    113------------------
    114- pins: List of pins. Valid values of pins properties are:
    115		      gpio0 ... gpio7 for the devices with 8 GPIO pins and
    116		      gpio0 ... gpio15 for the devices with 16 GPIO pins.
    117
    118Optional properties:
    119-------------------
    120The following optional property is defined in the pinmux DT binding document
    121<pinctrl-bindings.txt>. Absence of this property will leave the configuration
    122in its default state.
    123	bias-pull-up
    124
    125Example with pinctrl to pull-up output pins:
    126gpio21: gpio@21 {
    127	compatible = "microchip,mcp23017";
    128	gpio-controller;
    129	#gpio-cells = <0x2>;
    130	reg = <0x21>;
    131	interrupt-parent = <&socgpio>;
    132	interrupts = <0x17 0x8>;
    133	interrupt-names = "mcp23017@21 irq";
    134	interrupt-controller;
    135	#interrupt-cells = <0x2>;
    136	microchip,irq-mirror;
    137	pinctrl-names = "default";
    138	pinctrl-0 = <&i2cgpio0irq>, <&gpio21pullups>;
    139	reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
    140
    141	gpio21pullups: pinmux {
    142		pins =	"gpio0", "gpio1", "gpio2", "gpio3",
    143			"gpio4", "gpio5", "gpio6", "gpio7",
    144			"gpio8", "gpio9", "gpio10", "gpio11",
    145			"gpio12", "gpio13", "gpio14", "gpio15";
    146		bias-pull-up;
    147	};
    148};