cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,mdm9607-pinctrl.yaml (4776B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-pinctrl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Technologies, Inc. MDM9607 TLMM block
      8
      9maintainers:
     10  - Konrad Dybcio <konrad.dybcio@somainline.org>
     11
     12description: |
     13  This binding describes the Top Level Mode Multiplexer block found in the
     14  MDM9607 platform.
     15
     16allOf:
     17  - $ref: "pinctrl.yaml#"
     18  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
     19
     20properties:
     21  compatible:
     22    const: qcom,mdm9607-tlmm
     23
     24  reg:
     25    maxItems: 1
     26
     27  interrupts: true
     28  interrupt-controller: true
     29  '#interrupt-cells': true
     30  gpio-controller: true
     31  gpio-reserved-ranges: true
     32  '#gpio-cells': true
     33  gpio-ranges: true
     34  wakeup-parent: true
     35
     36required:
     37  - compatible
     38  - reg
     39
     40additionalProperties: false
     41
     42patternProperties:
     43  '-state$':
     44    oneOf:
     45      - $ref: "#/$defs/qcom-mdm9607-tlmm-state"
     46      - patternProperties:
     47          ".*":
     48            $ref: "#/$defs/qcom-mdm9607-tlmm-state"
     49
     50'$defs':
     51  qcom-mdm9607-tlmm-state:
     52    type: object
     53    description:
     54      Pinctrl node's client devices use subnodes for desired pin configuration.
     55      Client device subnodes use below standard properties.
     56    $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
     57
     58    properties:
     59      pins:
     60        description:
     61          List of gpio pins affected by the properties specified in this
     62          subnode.
     63        items:
     64          oneOf:
     65            - pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
     66            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
     67                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
     68                      qdsd_data3 ]
     69        minItems: 1
     70        maxItems: 16
     71
     72      function:
     73        description:
     74          Specify the alternative function to be configured for the specified
     75          pins.
     76
     77        enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
     78                atest_char1, atest_char2, atest_char3,
     79                atest_combodac_to_gpio_native, atest_gpsadc_dtest0_native,
     80                atest_gpsadc_dtest1_native, atest_tsens, backlight_en_b,
     81                bimc_dte0, bimc_dte1, blsp1_spi, blsp2_spi, blsp3_spi,
     82                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
     83                blsp_i2c6, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4,
     84                blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uart3,
     85                blsp_uart4, blsp_uart5, blsp_uart6, blsp_uim1, blsp_uim2,
     86                codec_int, codec_rst, coex_uart, cri_trng, cri_trng0,
     87                cri_trng1, dbg_out, ebi0_wrcdc, ebi2_a, ebi2_a_d_8_b,
     88                ebi2_lcd, ebi2_lcd_cs_n_b, ebi2_lcd_te_b, eth_irq, eth_rst,
     89                gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b,
     90                gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gmac_mdio,
     91                gpio, gsm0_tx, lcd_rst, ldo_en, ldo_update, m_voc, modem_tsync,
     92                nav_ptp_pps_in_a, nav_ptp_pps_in_b, nav_tsync_out_a,
     93                nav_tsync_out_b, pa_indicator, pbs0, pbs1, pbs2,
     94                pri_mi2s_data0_a, pri_mi2s_data1_a, pri_mi2s_mclk_a,
     95                pri_mi2s_sck_a, pri_mi2s_ws_a, prng_rosc, ptp_pps_out_a,
     96                ptp_pps_out_b, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
     97                pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
     98                pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
     99                qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
    100                qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
    101                qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
    102                qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, rcm_marker1,
    103                rcm_marker2, sd_write, sec_mi2s, sensor_en, sensor_int2,
    104                sensor_int3, sensor_rst, ssbi1, ssbi2, touch_rst, ts_int,
    105                uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
    106                uim2_data, uim2_present, uim2_reset, uim_batt, wlan_en1, ]
    107
    108      bias-disable: true
    109      bias-pull-down: true
    110      bias-pull-up: true
    111      drive-strength: true
    112      input-enable: true
    113      output-high: true
    114      output-low: true
    115
    116    required:
    117      - pins
    118      - function
    119
    120    additionalProperties: false
    121
    122examples:
    123  - |
    124        #include <dt-bindings/interrupt-controller/arm-gic.h>
    125        tlmm: pinctrl@1000000 {
    126          compatible = "qcom,mdm9607-tlmm";
    127          reg = <0x01000000 0x300000>;
    128          interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
    129          gpio-controller;
    130          gpio-ranges = <&msmgpio 0 0 80>;
    131          #gpio-cells = <2>;
    132          interrupt-controller;
    133          #interrupt-cells = <2>;
    134        };