cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,msm8226-pinctrl.yaml (3500B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Technologies, Inc. MSM8226 TLMM block
      8
      9maintainers:
     10  - Bjorn Andersson <bjorn.andersson@linaro.org>
     11
     12description: |
     13  This binding describes the Top Level Mode Multiplexer block found in the
     14  MSM8226 platform.
     15
     16properties:
     17  compatible:
     18    const: qcom,msm8226-pinctrl
     19
     20  reg:
     21    description: Specifies the base address and size of the TLMM register space
     22    maxItems: 1
     23
     24  interrupts:
     25    description: Specifies the TLMM summary IRQ
     26    maxItems: 1
     27
     28  interrupt-controller: true
     29
     30  '#interrupt-cells':
     31    description: Specifies the PIN numbers and Flags, as defined in
     32      include/dt-bindings/interrupt-controller/irq.h
     33    const: 2
     34
     35  gpio-controller: true
     36
     37  '#gpio-cells':
     38    description: Specifying the pin number and flags, as defined in
     39      include/dt-bindings/gpio/gpio.h
     40    const: 2
     41
     42  gpio-ranges:
     43    maxItems: 1
     44
     45  gpio-reserved-ranges:
     46    maxItems: 1
     47
     48#PIN CONFIGURATION NODES
     49patternProperties:
     50  '-pins$':
     51    type: object
     52    description:
     53      Pinctrl node's client devices use subnodes for desired pin configuration.
     54      Client device subnodes use below standard properties.
     55    $ref: "/schemas/pinctrl/pincfg-node.yaml"
     56
     57    properties:
     58      pins:
     59        description:
     60          List of gpio pins affected by the properties specified in this
     61          subnode.
     62        items:
     63          oneOf:
     64            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
     65            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
     66        minItems: 1
     67        maxItems: 36
     68
     69      function:
     70        description:
     71          Specify the alternative function to be configured for the specified
     72          pins. Functions are only valid for gpio pins.
     73        enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
     74                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c5, blsp_spi1,
     75                blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
     76                blsp_uart3, blsp_uart5, cam_mclk0, cam_mclk1, wlan ]
     77
     78      drive-strength:
     79        enum: [2, 4, 6, 8, 10, 12, 14, 16]
     80        default: 2
     81        description:
     82          Selects the drive strength for the specified pins, in mA.
     83
     84      bias-pull-down: true
     85
     86      bias-pull-up: true
     87
     88      bias-disable: true
     89
     90      output-high: true
     91
     92      output-low: true
     93
     94    required:
     95      - pins
     96      - function
     97
     98    additionalProperties: false
     99
    100allOf:
    101  - $ref: "pinctrl.yaml#"
    102
    103required:
    104  - compatible
    105  - reg
    106  - interrupts
    107  - interrupt-controller
    108  - '#interrupt-cells'
    109  - gpio-controller
    110  - '#gpio-cells'
    111  - gpio-ranges
    112
    113additionalProperties: false
    114
    115examples:
    116  - |
    117        #include <dt-bindings/interrupt-controller/arm-gic.h>
    118        msmgpio: pinctrl@fd510000 {
    119                compatible = "qcom,msm8226-pinctrl";
    120                reg = <0xfd510000 0x4000>;
    121
    122                gpio-controller;
    123                #gpio-cells = <2>;
    124                gpio-ranges = <&msmgpio 0 0 117>;
    125                interrupt-controller;
    126                #interrupt-cells = <2>;
    127                interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
    128
    129                serial-pins {
    130                        pins = "gpio8", "gpio9";
    131                        function = "blsp_uart3";
    132                        drive-strength = <8>;
    133                        bias-disable;
    134                };
    135        };