qcom,msm8996-pinctrl.txt (7528B)
1Qualcomm MSM8996 TLMM block 2 3This binding describes the Top Level Mode Multiplexer block found in the 4MSM8996 platform. 5 6- compatible: 7 Usage: required 8 Value type: <string> 9 Definition: must be "qcom,msm8996-pinctrl" 10 11- reg: 12 Usage: required 13 Value type: <prop-encoded-array> 14 Definition: the base address and size of the TLMM register space. 15 16- interrupts: 17 Usage: required 18 Value type: <prop-encoded-array> 19 Definition: should specify the TLMM summary IRQ. 20 21- interrupt-controller: 22 Usage: required 23 Value type: <none> 24 Definition: identifies this node as an interrupt controller 25 26- #interrupt-cells: 27 Usage: required 28 Value type: <u32> 29 Definition: must be 2. Specifying the pin number and flags, as defined 30 in <dt-bindings/interrupt-controller/irq.h> 31 32- gpio-controller: 33 Usage: required 34 Value type: <none> 35 Definition: identifies this node as a gpio controller 36 37- #gpio-cells: 38 Usage: required 39 Value type: <u32> 40 Definition: must be 2. Specifying the pin number and flags, as defined 41 in <dt-bindings/gpio/gpio.h> 42 43- gpio-ranges: 44 Usage: required 45 Definition: see ../gpio/gpio.txt 46 47- gpio-reserved-ranges: 48 Usage: optional 49 Definition: see ../gpio/gpio.txt 50 51Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for 52a general description of GPIO and interrupt bindings. 53 54Please refer to pinctrl-bindings.txt in this directory for details of the 55common pinctrl bindings used by client devices, including the meaning of the 56phrase "pin configuration node". 57 58The pin configuration nodes act as a container for an arbitrary number of 59subnodes. Each of these subnodes represents some desired configuration for a 60pin, a group, or a list of pins or groups. This configuration can include the 61mux function to select on those pin(s)/group(s), and various pin configuration 62parameters, such as pull-up, drive strength, etc. 63 64 65PIN CONFIGURATION NODES: 66 67The name of each subnode is not important; all subnodes should be enumerated 68and processed purely based on their content. 69 70Each subnode only affects those parameters that are explicitly listed. In 71other words, a subnode that lists a mux function but no pin configuration 72parameters implies no information about any pin configuration parameters. 73Similarly, a pin subnode that describes a pullup parameter implies no 74information about e.g. the mux function. 75 76 77The following generic properties as defined in pinctrl-bindings.txt are valid 78to specify in a pin configuration subnode: 79 80- pins: 81 Usage: required 82 Value type: <string-array> 83 Definition: List of gpio pins affected by the properties specified in 84 this subnode. 85 86 Valid pins are: 87 gpio0-gpio149 88 Supports mux, bias and drive-strength 89 90 sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, 91 sdc2_data sdc1_rclk 92 Supports bias and drive-strength 93 94- function: 95 Usage: required 96 Value type: <string> 97 Definition: Specify the alternative function to be configured for the 98 specified pins. Functions are only valid for gpio pins. 99 Valid values are: 100 101 blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, 102 bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, 103 qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, 104 dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, 105 blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, 106 mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, 107 atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, 108 cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, 109 pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, 110 qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, 111 qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, 112 atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, 113 atest_usb20, atest_char0, dac_calib10, qdss_stm10, 114 qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, 115 blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, 116 qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, 117 qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, 118 dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, 119 qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, 120 dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, 121 dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, 122 dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, 123 dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, 124 sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, 125 qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, 126 uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, 127 blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, 128 qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, 129 blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, 130 cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, 131 blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, 132 qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, 133 isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, 134 qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, 135 sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, 136 gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, 137 qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, 138 tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, 139 qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, 140 sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, 141 sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, 142 ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, 143 blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, 144 pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, 145 qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, 146 qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, 147 gpio 148 149- bias-disable: 150 Usage: optional 151 Value type: <none> 152 Definition: The specified pins should be configured as no pull. 153 154- bias-pull-down: 155 Usage: optional 156 Value type: <none> 157 Definition: The specified pins should be configured as pull down. 158 159- bias-pull-up: 160 Usage: optional 161 Value type: <none> 162 Definition: The specified pins should be configured as pull up. 163 164- output-high: 165 Usage: optional 166 Value type: <none> 167 Definition: The specified pins are configured in output mode, driven 168 high. 169 Not valid for sdc pins. 170 171- output-low: 172 Usage: optional 173 Value type: <none> 174 Definition: The specified pins are configured in output mode, driven 175 low. 176 Not valid for sdc pins. 177 178- drive-strength: 179 Usage: optional 180 Value type: <u32> 181 Definition: Selects the drive strength for the specified pins, in mA. 182 Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 183 184Example: 185 186 tlmm: pinctrl@1010000 { 187 compatible = "qcom,msm8996-pinctrl"; 188 reg = <0x01010000 0x300000>; 189 interrupts = <0 208 0>; 190 gpio-controller; 191 gpio-ranges = <&tlmm 0 0 150>; 192 #gpio-cells = <2>; 193 interrupt-controller; 194 #interrupt-cells = <2>; 195 196 uart_console_active: uart_console_active { 197 mux { 198 pins = "gpio4", "gpio5"; 199 function = "blsp_uart8"; 200 }; 201 202 config { 203 pins = "gpio4", "gpio5"; 204 drive-strength = <2>; 205 bias-disable; 206 }; 207 }; 208 };