cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,qcm2290-pinctrl.yaml (4641B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/pinctrl/qcom,qcm2290-pinctrl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Technologies, Inc. QCM2290 TLMM block
      8
      9maintainers:
     10  - Shawn Guo <shawn.guo@linaro.org>
     11
     12description:
     13  This binding describes the Top Level Mode Multiplexer block found in the
     14  QCM2290 platform.
     15
     16properties:
     17  compatible:
     18    const: qcom,qcm2290-tlmm
     19
     20  reg:
     21    maxItems: 1
     22
     23  interrupts:
     24    description: Specifies the TLMM summary IRQ
     25    maxItems: 1
     26
     27  interrupt-controller: true
     28
     29  '#interrupt-cells':
     30    description:
     31      Specifies the PIN numbers and Flags, as defined in defined in
     32      include/dt-bindings/interrupt-controller/irq.h
     33    const: 2
     34
     35  gpio-controller: true
     36
     37  '#gpio-cells':
     38    description: Specifying the pin number and flags, as defined in
     39      include/dt-bindings/gpio/gpio.h
     40    const: 2
     41
     42  gpio-ranges:
     43    maxItems: 1
     44
     45  wakeup-parent: true
     46
     47#PIN CONFIGURATION NODES
     48patternProperties:
     49  '-state$':
     50    oneOf:
     51      - $ref: "#/$defs/qcom-qcm2290-tlmm-state"
     52      - patternProperties:
     53          ".*":
     54            $ref: "#/$defs/qcom-qcm2290-tlmm-state"
     55
     56'$defs':
     57  qcom-qcm2290-tlmm-state:
     58    type: object
     59    description:
     60      Pinctrl node's client devices use subnodes for desired pin configuration.
     61      Client device subnodes use below standard properties.
     62    $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
     63
     64    properties:
     65      pins:
     66        description:
     67          List of gpio pins affected by the properties specified in this
     68          subnode.
     69        items:
     70          oneOf:
     71            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-6])$"
     72            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
     73                      sdc2_clk, sdc2_cmd, sdc2_data ]
     74        minItems: 1
     75        maxItems: 36
     76
     77      function:
     78        description:
     79          Specify the alternative function to be configured for the specified
     80          pins.
     81
     82        enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
     83                cci_timer0, cci_timer1, cci_timer2, cci_timer3, char_exec,
     84                cri_trng, cri_trng0, cri_trng1, dac_calib, dbg_out, ddr_bist,
     85                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2,
     86                gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx,
     87                jitter_bist, mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1,
     88                mpm_pwr, mss_lte, m_voc, nav_gpio, pa_indicator, pbs0, pbs1,
     89                pbs2, pbs3, pbs4, pbs5, pbs6, pbs7, pbs8, pbs9, pbs10, pbs11,
     90                pbs12, pbs13, pbs14, pbs15, pbs_out, phase_flag, pll_bist,
     91                pll_bypassnl, pll_reset, prng_rosc, pwm_0, pwm_1, pwm_2, pwm_3,
     92                pwm_4, pwm_5, pwm_6, pwm_7, pwm_8, pwm_9, qdss_cti, qdss_gpio,
     93                qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb, sdc2_tb, sd_write,
     94                ssbi_wtr1, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm,
     95                uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
     96                uim2_data, uim2_present, uim2_reset, usb_phy, vfr_1,
     97                vsense_trigger, wlan1_adc0, wlan1_adc1 ]
     98
     99      drive-strength:
    100        enum: [2, 4, 6, 8, 10, 12, 14, 16]
    101        default: 2
    102        description:
    103          Selects the drive strength for the specified pins, in mA.
    104
    105      bias-pull-down: true
    106
    107      bias-pull-up: true
    108
    109      bias-disable: true
    110
    111      output-high: true
    112
    113      output-low: true
    114
    115    required:
    116      - pins
    117
    118    additionalProperties: false
    119
    120allOf:
    121  - $ref: "pinctrl.yaml#"
    122
    123required:
    124  - compatible
    125  - reg
    126  - interrupts
    127  - interrupt-controller
    128  - '#interrupt-cells'
    129  - gpio-controller
    130  - '#gpio-cells'
    131  - gpio-ranges
    132
    133additionalProperties: false
    134
    135examples:
    136  - |
    137    #include <dt-bindings/interrupt-controller/arm-gic.h>
    138    tlmm: pinctrl@500000 {
    139        compatible = "qcom,qcm2290-tlmm";
    140        reg = <0x500000 0x300000>;
    141        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
    142        gpio-controller;
    143        #gpio-cells = <2>;
    144        interrupt-controller;
    145        #interrupt-cells = <2>;
    146        gpio-ranges = <&tlmm 0 0 127>;
    147
    148        sdc2_on_state: sdc2-on-state {
    149            clk {
    150                pins = "sdc2_clk";
    151                bias-disable;
    152                drive-strength = <16>;
    153            };
    154
    155            cmd {
    156                pins = "sdc2_cmd";
    157                bias-pull-up;
    158                drive-strength = <10>;
    159            };
    160
    161            data {
    162                pins = "sdc2_data";
    163                bias-pull-up;
    164                drive-strength = <10>;
    165            };
    166        };
    167    };