cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,sc7280-pinctrl.yaml (5197B)


      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Technologies, Inc. SC7280 TLMM block
      8
      9maintainers:
     10  - Rajendra Nayak <rnayak@codeaurora.org>
     11
     12description: |
     13  This binding describes the Top Level Mode Multiplexer block found in the
     14  SC7280 platform.
     15
     16properties:
     17  compatible:
     18    const: qcom,sc7280-pinctrl
     19
     20  reg:
     21    maxItems: 1
     22
     23  interrupts:
     24    description: Specifies the TLMM summary IRQ
     25    maxItems: 1
     26
     27  interrupt-controller: true
     28
     29  '#interrupt-cells':
     30    description:
     31      Specifies the PIN numbers and Flags, as defined in defined in
     32      include/dt-bindings/interrupt-controller/irq.h
     33    const: 2
     34
     35  gpio-controller: true
     36
     37  '#gpio-cells':
     38    description: Specifying the pin number and flags, as defined in
     39      include/dt-bindings/gpio/gpio.h
     40    const: 2
     41
     42  gpio-ranges:
     43    maxItems: 1
     44
     45  wakeup-parent: true
     46
     47#PIN CONFIGURATION NODES
     48patternProperties:
     49  '-pins$':
     50    type: object
     51    description:
     52      Pinctrl node's client devices use subnodes for desired pin configuration.
     53      Client device subnodes use below standard properties.
     54    $ref: "/schemas/pinctrl/pincfg-node.yaml"
     55
     56    properties:
     57      pins:
     58        description:
     59          List of gpio pins affected by the properties specified in this
     60          subnode.
     61        items:
     62          oneOf:
     63            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-4])$"
     64            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
     65                      sdc2_cmd, sdc2_data, ufs_reset ]
     66        minItems: 1
     67        maxItems: 16
     68
     69      function:
     70        description:
     71          Specify the alternative function to be configured for the specified
     72          pins.
     73
     74        enum: [ atest_char, atest_char0, atest_char1, atest_char2,
     75                atest_char3, atest_usb0, atest_usb00, atest_usb01,
     76                atest_usb02, atest_usb03, atest_usb1, atest_usb10,
     77                atest_usb11, atest_usb12, atest_usb13, audio_ref,
     78                cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
     79                cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1,
     80                cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0,
     81                cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot,
     82                dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
     83                gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus,
     84                mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
     85                mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck,
     86                mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
     87                mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0,
     88                mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2,
     89                mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7,
     90                mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2,
     91                pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag,
     92                pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
     93                qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss,
     94                qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs,
     95                qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07,
     96                qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
     97                sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write,
     98                sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1,
     99                tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset,
    100                uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
    101                usb_phy, vfr_0, vfr_1, vsense_trigger ]
    102
    103      drive-strength:
    104        enum: [2, 4, 6, 8, 10, 12, 14, 16]
    105        default: 2
    106        description:
    107          Selects the drive strength for the specified pins, in mA.
    108
    109      bias-pull-down: true
    110
    111      bias-pull-up: true
    112
    113      bias-disable: true
    114
    115      output-high: true
    116
    117      output-low: true
    118
    119    required:
    120      - pins
    121      - function
    122
    123    additionalProperties: false
    124
    125allOf:
    126  - $ref: "pinctrl.yaml#"
    127
    128required:
    129  - compatible
    130  - reg
    131  - interrupts
    132  - interrupt-controller
    133  - '#interrupt-cells'
    134  - gpio-controller
    135  - '#gpio-cells'
    136  - gpio-ranges
    137
    138additionalProperties: false
    139
    140examples:
    141  - |
    142        #include <dt-bindings/interrupt-controller/arm-gic.h>
    143        tlmm: pinctrl@f000000 {
    144                compatible = "qcom,sc7280-pinctrl";
    145                reg = <0xf000000 0x1000000>;
    146                interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
    147                gpio-controller;
    148                #gpio-cells = <2>;
    149                interrupt-controller;
    150                #interrupt-cells = <2>;
    151                gpio-ranges = <&tlmm 0 0 175>;
    152                wakeup-parent = <&pdc>;
    153
    154                qup_uart5_default: qup-uart5-pins {
    155                        pins = "gpio46", "gpio47";
    156                        function = "qup13";
    157                        drive-strength = <2>;
    158                        bias-disable;
    159                };
    160        };