qcom,sdm660-pinctrl.txt (6973B)
1Qualcomm Technologies, Inc. SDM660 TLMM block 2 3This binding describes the Top Level Mode Multiplexer block found in the 4SDM660 platform. 5 6- compatible: 7 Usage: required 8 Value type: <string> 9 Definition: must be "qcom,sdm660-pinctrl" or 10 "qcom,sdm630-pinctrl". 11 12- reg: 13 Usage: required 14 Value type: <prop-encoded-array> 15 Definition: the base address and size of the north, center and south 16 TLMM tiles. 17 18- reg-names: 19 Usage: required 20 Value type: <stringlist> 21 Definition: names for the cells of reg, must contain "north", "center" 22 and "south". 23 24- interrupts: 25 Usage: required 26 Value type: <prop-encoded-array> 27 Definition: should specify the TLMM summary IRQ. 28 29- interrupt-controller: 30 Usage: required 31 Value type: <none> 32 Definition: identifies this node as an interrupt controller 33 34- #interrupt-cells: 35 Usage: required 36 Value type: <u32> 37 Definition: must be 2. Specifying the pin number and flags, as defined 38 in <dt-bindings/interrupt-controller/irq.h> 39 40- gpio-controller: 41 Usage: required 42 Value type: <none> 43 Definition: identifies this node as a gpio controller 44 45- gpio-ranges: 46 Usage: required 47 Value type: <prop-encoded-array> 48 Definition: Specifies the mapping between gpio controller and 49 pin-controller pins. 50 51- #gpio-cells: 52 Usage: required 53 Value type: <u32> 54 Definition: must be 2. Specifying the pin number and flags, as defined 55 in <dt-bindings/gpio/gpio.h> 56 57Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for 58a general description of GPIO and interrupt bindings. 59 60Please refer to pinctrl-bindings.txt in this directory for details of the 61common pinctrl bindings used by client devices, including the meaning of the 62phrase "pin configuration node". 63 64The pin configuration nodes act as a container for an arbitrary number of 65subnodes. Each of these subnodes represents some desired configuration for a 66pin, a group, or a list of pins or groups. This configuration can include the 67mux function to select on those pin(s)/group(s), and various pin configuration 68parameters, such as pull-up, drive strength, etc. 69 70 71PIN CONFIGURATION NODES: 72 73The name of each subnode is not important; all subnodes should be enumerated 74and processed purely based on their content. 75 76Each subnode only affects those parameters that are explicitly listed. In 77other words, a subnode that lists a mux function but no pin configuration 78parameters implies no information about any pin configuration parameters. 79Similarly, a pin subnode that describes a pullup parameter implies no 80information about e.g. the mux function. 81 82 83The following generic properties as defined in pinctrl-bindings.txt are valid 84to specify in a pin configuration subnode: 85 86- pins: 87 Usage: required 88 Value type: <string-array> 89 Definition: List of gpio pins affected by the properties specified in 90 this subnode. Valid pins are: 91 gpio0-gpio113, 92 Supports mux, bias and drive-strength 93 sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, sdc2_data sdc1_rclk, 94 Supports bias and drive-strength 95 96- function: 97 Usage: required 98 Value type: <string> 99 Definition: Specify the alternative function to be configured for the 100 specified pins. Functions are only valid for gpio pins. 101 Valid values are: 102 adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, 103 atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1, 104 atest_tsens, atest_tsens2, atest_usb1, atest_usb10, 105 atest_usb11, atest_usb12, atest_usb13, atest_usb2, 106 atest_usb20, atest_usb21, atest_usb22, atest_usb23, 107 audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2, 108 blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, 109 blsp_i2c8_a, blsp_i2c8_b, blsp_spi1, blsp_spi2, blsp_spi3, 110 blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi4, blsp_spi5, 111 blsp_spi6, blsp_spi7, blsp_spi8_a, blsp_spi8_b, 112 blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1, blsp_uart2, 113 blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1, 114 blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async, 115 cci_i2c, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, 116 gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c, 117 isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync, 118 mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte, 119 nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0, 120 phase_flag1, phase_flag10, phase_flag11, phase_flag12, 121 phase_flag13, phase_flag14, phase_flag15, phase_flag16, 122 phase_flag17, phase_flag18, phase_flag19, phase_flag2, 123 phase_flag20, phase_flag21, phase_flag22, phase_flag23, 124 phase_flag24, phase_flag25, phase_flag26, phase_flag27, 125 phase_flag28, phase_flag29, phase_flag3, phase_flag30, 126 phase_flag31, phase_flag4, phase_flag5, phase_flag6, 127 phase_flag7, phase_flag8, phase_flag9, pll_bypassnl, 128 pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, 129 pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, 130 qdss_cti1_b, qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, 131 qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, 132 qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, 133 qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request, 134 qspi_clk, qspi_cs, qspi_data0, qspi_data1, qspi_data2, 135 qspi_data3, qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data, 136 sp_cmu, ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, 137 uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, 138 uim2_data, uim2_present, uim2_reset, uim_batt, vfr_1, 139 vsense_clkout, vsense_data0, vsense_data1, vsense_mode, 140 wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1 141 142- bias-disable: 143 Usage: optional 144 Value type: <none> 145 Definition: The specified pins should be configured as no pull. 146 147- bias-pull-down: 148 Usage: optional 149 Value type: <none> 150 Definition: The specified pins should be configured as pull down. 151 152- bias-pull-up: 153 Usage: optional 154 Value type: <none> 155 Definition: The specified pins should be configured as pull up. 156 157- output-high: 158 Usage: optional 159 Value type: <none> 160 Definition: The specified pins are configured in output mode, driven 161 high. 162 Not valid for sdc pins. 163 164- output-low: 165 Usage: optional 166 Value type: <none> 167 Definition: The specified pins are configured in output mode, driven 168 low. 169 Not valid for sdc pins. 170 171- drive-strength: 172 Usage: optional 173 Value type: <u32> 174 Definition: Selects the drive strength for the specified pins, in mA. 175 Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 176 177Example: 178 179 tlmm: pinctrl@3100000 { 180 compatible = "qcom,sdm660-pinctrl"; 181 reg = <0x3100000 0x200000>, 182 <0x3500000 0x200000>, 183 <0x3900000 0x200000>; 184 reg-names = "south", "center", "north"; 185 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 186 gpio-controller; 187 gpio-ranges = <&tlmm 0 0 114>; 188 #gpio-cells = <2>; 189 interrupt-controller; 190 #interrupt-cells = <2>; 191 };