cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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renesas,rza2-pinctrl.yaml (2918B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Renesas RZ/A2 combined Pin and GPIO controller
      8
      9maintainers:
     10  - Chris Brandt <chris.brandt@renesas.com>
     11  - Geert Uytterhoeven <geert+renesas@glider.be>
     12
     13description:
     14  The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
     15  controller.
     16  Pin multiplexing and GPIO configuration is performed on a per-pin basis.
     17  Each port features up to 8 pins, each of them configurable for GPIO function
     18  (port mode) or in alternate function mode.
     19  Up to 8 different alternate function modes exist for each single pin.
     20
     21properties:
     22  compatible:
     23    const: "renesas,r7s9210-pinctrl" # RZ/A2M
     24
     25  reg:
     26    maxItems: 1
     27
     28  gpio-controller: true
     29
     30  '#gpio-cells':
     31    const: 2
     32    description:
     33      The first cell contains the global GPIO port index, constructed using the
     34      RZA2_PIN() helper macro in r7s9210-pinctrl.h.
     35      E.g. "RZA2_PIN(PORT6, 0)" for P6_0.
     36
     37  gpio-ranges:
     38    maxItems: 1
     39
     40patternProperties:
     41  "^.*$":
     42    if:
     43      type: object
     44    then:
     45      allOf:
     46        - $ref: pincfg-node.yaml#
     47        - $ref: pinmux-node.yaml#
     48      description:
     49        The child nodes of the pin controller designate pins to be used for
     50        specific peripheral functions or as GPIO.
     51
     52        A pin multiplexing sub-node describes how to configure a set of
     53        (or a single) pin in some desired alternate function mode.
     54        The values for the pinmux properties are a combination of port name,
     55        pin number and the desired function index. Use the RZA2_PINMUX macro
     56        located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily
     57        define these.
     58        For assigning GPIO pins, use the macro RZA2_PIN also in
     59        to express the desired port pin.
     60
     61      properties:
     62        phandle: true
     63
     64        pinmux:
     65          description:
     66            Values are constructed from GPIO port number, pin number, and
     67            alternate function configuration number using the RZA2_PINMUX()
     68            helper macro in r7s9210-pinctrl.h.
     69
     70      required:
     71        - pinmux
     72
     73      additionalProperties: false
     74
     75allOf:
     76  - $ref: "pinctrl.yaml#"
     77
     78required:
     79  - compatible
     80  - reg
     81  - gpio-controller
     82  - '#gpio-cells'
     83  - gpio-ranges
     84
     85additionalProperties: false
     86
     87examples:
     88  - |
     89    #include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
     90    pinctrl: pinctrl@fcffe000 {
     91            compatible = "renesas,r7s9210-pinctrl";
     92            reg = <0xfcffe000 0x1000>;
     93
     94            gpio-controller;
     95            #gpio-cells = <2>;
     96            gpio-ranges = <&pinctrl 0 0 176>;
     97
     98            /* Serial Console */
     99            scif4_pins: serial4 {
    100                    pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
    101                             <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
    102            };
    103    };