cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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samsung,pinctrl-gpio-bank.yaml (1379B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-gpio-bank.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank
      8
      9maintainers:
     10  - Krzysztof Kozlowski <krzk@kernel.org>
     11  - Sylwester Nawrocki <s.nawrocki@samsung.com>
     12  - Tomasz Figa <tomasz.figa@gmail.com>
     13
     14description: |
     15  This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
     16  controller.
     17
     18  GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller.
     19
     20  See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for
     21  additional information and example.
     22
     23properties:
     24  '#gpio-cells':
     25    const: 2
     26
     27  gpio-controller: true
     28
     29  '#interrupt-cells':
     30    description:
     31      For GPIO banks supporting external GPIO interrupts or external wake-up
     32      interrupts.
     33    const: 2
     34
     35  interrupt-controller:
     36    description:
     37      For GPIO banks supporting external GPIO interrupts or external wake-up
     38      interrupts.
     39
     40  interrupts:
     41    description:
     42      For GPIO banks supporting direct external wake-up interrupts (without
     43      multiplexing).  Number of interrupts must match number of wake-up capable
     44      pins of this bank.
     45    minItems: 1
     46    maxItems: 8
     47
     48required:
     49  - '#gpio-cells'
     50  - gpio-controller
     51
     52additionalProperties: false