st,stm32-pinctrl.yaml (8127B)
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2# Copyright (C) STMicroelectronics 2019. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: STM32 GPIO and Pin Mux/Config controller 9 10maintainers: 11 - Alexandre TORGUE <alexandre.torgue@foss.st.com> 12 13description: | 14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware 15 controller. It controls the input/output settings on the available pins and 16 also provides ability to multiplex and configure the output of various 17 on-chip controllers onto these pads. 18 19properties: 20 compatible: 21 enum: 22 - st,stm32f429-pinctrl 23 - st,stm32f469-pinctrl 24 - st,stm32f746-pinctrl 25 - st,stm32f769-pinctrl 26 - st,stm32h743-pinctrl 27 - st,stm32mp135-pinctrl 28 - st,stm32mp157-pinctrl 29 - st,stm32mp157-z-pinctrl 30 31 '#address-cells': 32 const: 1 33 '#size-cells': 34 const: 1 35 36 ranges: true 37 pins-are-numbered: true 38 hwlocks: true 39 40 interrupts: 41 maxItems: 1 42 43 st,syscfg: 44 description: Phandle+args to the syscon node which includes IRQ mux selection. 45 $ref: "/schemas/types.yaml#/definitions/phandle-array" 46 items: 47 - items: 48 - description: syscon node which includes IRQ mux selection 49 - description: The offset of the IRQ mux selection register 50 - description: The field mask of IRQ mux, needed if different of 0xf 51 52 st,package: 53 description: 54 Indicates the SOC package used. 55 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h 56 $ref: /schemas/types.yaml#/definitions/uint32 57 enum: [1, 2, 4, 8] 58 59patternProperties: 60 '^gpio@[0-9a-f]*$': 61 type: object 62 properties: 63 gpio-controller: true 64 '#gpio-cells': 65 const: 2 66 67 reg: 68 maxItems: 1 69 clocks: 70 maxItems: 1 71 reset: 72 minItems: 1 73 maxItems: 1 74 gpio-ranges: 75 minItems: 1 76 maxItems: 16 77 ngpios: 78 description: 79 Number of available gpios in a bank. 80 minimum: 1 81 maximum: 16 82 83 st,bank-name: 84 description: 85 Should be a name string for this bank as specified in the datasheet. 86 $ref: "/schemas/types.yaml#/definitions/string" 87 enum: 88 - GPIOA 89 - GPIOB 90 - GPIOC 91 - GPIOD 92 - GPIOE 93 - GPIOF 94 - GPIOG 95 - GPIOH 96 - GPIOI 97 - GPIOJ 98 - GPIOK 99 - GPIOZ 100 101 st,bank-ioport: 102 description: 103 Should correspond to the EXTI IOport selection (EXTI line used 104 to select GPIOs as interrupts). 105 $ref: "/schemas/types.yaml#/definitions/uint32" 106 minimum: 0 107 maximum: 11 108 109 required: 110 - gpio-controller 111 - '#gpio-cells' 112 - reg 113 - clocks 114 - st,bank-name 115 116 '-[0-9]*$': 117 type: object 118 patternProperties: 119 '^pins': 120 type: object 121 description: | 122 A pinctrl node should contain at least one subnode representing the 123 pinctrl group available on the machine. Each subnode will list the 124 pins it needs, and how they should be configured, with regard to muxer 125 configuration, pullups, drive, output high/low and output speed. 126 properties: 127 pinmux: 128 $ref: "/schemas/types.yaml#/definitions/uint32-array" 129 description: | 130 Integer array, represents gpio pin number and mux setting. 131 Supported pin number and mux varies for different SoCs, and are 132 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly. 133 These defines are calculated as: ((port * 16 + line) << 8) | function 134 With: 135 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) 136 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) 137 - function: The function number, can be: 138 * 0 : GPIO 139 * 1 : Alternate Function 0 140 * 2 : Alternate Function 1 141 * 3 : Alternate Function 2 142 * ... 143 * 16 : Alternate Function 15 144 * 17 : Analog 145 To simplify the usage, macro is available to generate "pinmux" field. 146 This macro is available here: 147 - include/dt-bindings/pinctrl/stm32-pinfunc.h 148 Some examples of using macro: 149 /* GPIO A9 set as alernate function 2 */ 150 ... { 151 pinmux = <STM32_PINMUX('A', 9, AF2)>; 152 }; 153 /* GPIO A9 set as GPIO */ 154 ... { 155 pinmux = <STM32_PINMUX('A', 9, GPIO)>; 156 }; 157 /* GPIO A9 set as analog */ 158 ... { 159 pinmux = <STM32_PINMUX('A', 9, ANALOG)>; 160 }; 161 162 bias-disable: 163 type: boolean 164 bias-pull-down: 165 type: boolean 166 bias-pull-up: 167 type: boolean 168 drive-push-pull: 169 type: boolean 170 drive-open-drain: 171 type: boolean 172 output-low: 173 type: boolean 174 output-high: 175 type: boolean 176 slew-rate: 177 description: | 178 0: Low speed 179 1: Medium speed 180 2: Fast speed 181 3: High speed 182 $ref: /schemas/types.yaml#/definitions/uint32 183 enum: [0, 1, 2, 3] 184 185 required: 186 - pinmux 187 188allOf: 189 - $ref: "pinctrl.yaml#" 190 191required: 192 - compatible 193 - '#address-cells' 194 - '#size-cells' 195 - ranges 196 - pins-are-numbered 197 198additionalProperties: false 199 200examples: 201 - | 202 #include <dt-bindings/pinctrl/stm32-pinfunc.h> 203 #include <dt-bindings/mfd/stm32f4-rcc.h> 204 //Example 1 205 pinctrl@40020000 { 206 #address-cells = <1>; 207 #size-cells = <1>; 208 compatible = "st,stm32f429-pinctrl"; 209 ranges = <0 0x40020000 0x3000>; 210 pins-are-numbered; 211 212 gpioa: gpio@0 { 213 gpio-controller; 214 #gpio-cells = <2>; 215 reg = <0x0 0x400>; 216 resets = <&reset_ahb1 0>; 217 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; 218 st,bank-name = "GPIOA"; 219 }; 220 }; 221 222 //Example 2 (using gpio-ranges) 223 pinctrl@50020000 { 224 #address-cells = <1>; 225 #size-cells = <1>; 226 compatible = "st,stm32f429-pinctrl"; 227 ranges = <0 0x50020000 0x3000>; 228 pins-are-numbered; 229 230 gpiob: gpio@1000 { 231 gpio-controller; 232 #gpio-cells = <2>; 233 reg = <0x1000 0x400>; 234 resets = <&reset_ahb1 0>; 235 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; 236 st,bank-name = "GPIOB"; 237 gpio-ranges = <&pinctrl 0 0 16>; 238 }; 239 240 gpioc: gpio@2000 { 241 gpio-controller; 242 #gpio-cells = <2>; 243 reg = <0x2000 0x400>; 244 resets = <&reset_ahb1 0>; 245 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; 246 st,bank-name = "GPIOC"; 247 ngpios = <5>; 248 gpio-ranges = <&pinctrl 0 16 3>, 249 <&pinctrl 14 30 2>; 250 }; 251 }; 252 253 //Example 3 pin groups 254 pinctrl { 255 usart1_pins_a: usart1-0 { 256 pins1 { 257 pinmux = <STM32_PINMUX('A', 9, AF7)>; 258 bias-disable; 259 drive-push-pull; 260 slew-rate = <0>; 261 }; 262 pins2 { 263 pinmux = <STM32_PINMUX('A', 10, AF7)>; 264 bias-disable; 265 }; 266 }; 267 }; 268 269 usart1 { 270 pinctrl-0 = <&usart1_pins_a>; 271 pinctrl-names = "default"; 272 }; 273 274...