cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,da850-pupd.txt (1319B)


      1* Pin configuration for TI DA850/OMAP-L138/AM18x
      2
      3These SoCs have a separate controller for setting bias (internal pullup/down).
      4Bias can only be selected for groups rather than individual pins.
      5
      6Required Properties:
      7
      8  - compatible: Must be "ti,da850-pupd"
      9  - reg: Base address and length of the memory resource used by the pullup/down
     10    controller hardware module.
     11
     12The controller node also acts as a container for pin group configuration nodes.
     13The names of these groups are ignored.
     14
     15Pin Group Node Properties:
     16
     17- groups: An array of strings, each string containing the name of a pin group.
     18          Valid names are "cp0".."cp31".
     19
     20The pin configuration parameters use the generic pinconf bindings defined in
     21pinctrl-bindings.txt in this directory. The supported parameters are
     22bias-disable, bias-pull-up, bias-pull-down.
     23
     24
     25Example
     26-------
     27
     28In common dtsi file:
     29
     30	pinconf: pin-controller@22c00c {
     31		compatible = "ti,da850-pupd";
     32		reg = <0x22c00c 0x8>;
     33	};
     34
     35In board-specific file:
     36
     37	&pinconf {
     38		pinctrl-0 = <&pinconf_bias_groups>;
     39		pinctrl-names = "default";
     40
     41		pinconf_bias_groups: bias-groups {
     42			pull-up {
     43				groups = "cp30", "cp31";
     44				bias-pull-up;
     45			};
     46			pull-down {
     47				groups = "cp29", "cp28";
     48				bias-pull-down;
     49			};
     50			disable {
     51				groups = "cp27", "cp26";
     52				bias-disable;
     53			};
     54		};
     55	};