cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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amlogic,meson-gx-pwrc.txt (1926B)

      1Amlogic Meson Power Controller
      2==============================
      3
      4The Amlogic Meson SoCs embeds an internal Power domain controller.
      5
      6VPU Power Domain
      7----------------
      8
      9The Video Processing Unit power domain is controlled by this power controller,
     10but the domain requires some external resources to meet the correct power
     11sequences.
     12The bindings must respect the power domain bindings as described in the file
     13power-domain.yaml
     14
     15Device Tree Bindings:
     16---------------------
     17
     18Required properties:
     19- compatible: should be one of the following :
     20	- "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
     21	- "amlogic,meson-g12a-pwrc-vpu" for the Meson G12A SoCs
     22- #power-domain-cells: should be 0
     23- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
     24- resets: phandles to the reset lines needed for this power demain sequence
     25	as described in ../reset/reset.txt
     26- clocks: from common clock binding: handle to VPU and VAPB clocks
     27- clock-names: from common clock binding: must contain "vpu", "vapb"
     28	corresponding to entry in the clocks property.
     29
     30Parent node should have the following properties :
     31- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
     32- reg: base address and size of the AO system control register space.
     33
     34Example:
     35-------
     36
     37ao_sysctrl: sys-ctrl@0 {
     38	compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
     39	reg =  <0x0 0x0 0x0 0x100>;
     40
     41	pwrc_vpu: power-controller-vpu {
     42		compatible = "amlogic,meson-gx-pwrc-vpu";
     43		#power-domain-cells = <0>;
     44		amlogic,hhi-sysctrl = <&sysctrl>;
     45		resets = <&reset RESET_VIU>,
     46			 <&reset RESET_VENC>,
     47			 <&reset RESET_VCBUS>,
     48			 <&reset RESET_BT656>,
     49			 <&reset RESET_DVIN_RESET>,
     50			 <&reset RESET_RDMA>,
     51			 <&reset RESET_VENCI>,
     52			 <&reset RESET_VENCP>,
     53			 <&reset RESET_VDAC>,
     54			 <&reset RESET_VDI6>,
     55			 <&reset RESET_VENCL>,
     56			 <&reset RESET_VID_LOCK>;
     57		clocks = <&clkc CLKID_VPU>,
     58			 <&clkc CLKID_VAPB>;
     59		clock-names = "vpu", "vapb";
     60	};
     61};
     62
     63