cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,imx-gpcv2.yaml (3526B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/power/fsl,imx-gpcv2.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Freescale i.MX General Power Controller v2
      8
      9maintainers:
     10  - Andrey Smirnov <andrew.smirnov@gmail.com>
     11
     12description: |
     13  The i.MX7S/D General Power Control (GPC) block contains Power Gating
     14  Control (PGC) for various power domains.
     15
     16  Power domains contained within GPC node are generic power domain
     17  providers, documented in
     18  Documentation/devicetree/bindings/power/power-domain.yaml, which are
     19  described as subnodes of the power gating controller 'pgc' node.
     20
     21  IP cores belonging to a power domain should contain a 'power-domains'
     22  property that is a phandle for PGC node representing the domain.
     23
     24properties:
     25  compatible:
     26    enum:
     27      - fsl,imx7d-gpc
     28      - fsl,imx8mn-gpc
     29      - fsl,imx8mq-gpc
     30      - fsl,imx8mm-gpc
     31      - fsl,imx8mp-gpc
     32
     33  reg:
     34    maxItems: 1
     35
     36  interrupts:
     37    maxItems: 1
     38
     39  interrupt-controller: true
     40  '#interrupt-cells':
     41    const: 3
     42
     43  pgc:
     44    type: object
     45    description: list of power domains provided by this controller.
     46
     47    patternProperties:
     48      "power-domain@[0-9]$":
     49        type: object
     50        properties:
     51
     52          '#power-domain-cells':
     53            const: 0
     54
     55          reg:
     56            description: |
     57              Power domain index. Valid values are defined in
     58              include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
     59              include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
     60              include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc
     61              include/dt-bindings/power/imx8mp-power.h for fsl,imx8mp-gpc
     62            maxItems: 1
     63
     64          clocks:
     65            description: |
     66              A number of phandles to clocks that need to be enabled during domain
     67              power-up sequencing to ensure reset propagation into devices located
     68              inside this power domain.
     69            minItems: 1
     70            maxItems: 5
     71
     72          power-supply: true
     73
     74          resets:
     75            description: |
     76              A number of phandles to resets that need to be asserted during
     77              power-up sequencing of the domain. The resets belong to devices
     78              located inside the power domain, which need to be held in reset
     79              across the power-up sequence. So no means to specify what each
     80              reset is in a generic power-domain binding.
     81            minItems: 1
     82            maxItems: 4
     83
     84        required:
     85          - '#power-domain-cells'
     86          - reg
     87
     88required:
     89  - compatible
     90  - reg
     91  - interrupts
     92  - pgc
     93
     94additionalProperties: false
     95
     96examples:
     97  - |
     98    #include <dt-bindings/interrupt-controller/arm-gic.h>
     99
    100    gpc@303a0000 {
    101        compatible = "fsl,imx7d-gpc";
    102        reg = <0x303a0000 0x1000>;
    103        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
    104
    105        pgc {
    106            #address-cells = <1>;
    107            #size-cells = <0>;
    108
    109            pgc_mipi_phy: power-domain@0 {
    110                #power-domain-cells = <0>;
    111                reg = <0>;
    112                power-supply = <&reg_1p0d>;
    113            };
    114
    115            pgc_pcie_phy: power-domain@1 {
    116                #power-domain-cells = <0>;
    117                reg = <1>;
    118                power-supply = <&reg_1p0d>;
    119            };
    120
    121            pgc_hsic_phy: power-domain@2 {
    122                #power-domain-cells = <0>;
    123                reg = <2>;
    124                power-supply = <&reg_1p2>;
    125            };
    126        };
    127    };