cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cpm.txt (1865B)


      1PPC4xx Clock Power Management (CPM) node
      2
      3Required properties:
      4	- compatible		: compatible list, currently only "ibm,cpm"
      5	- dcr-access-method	: "native"
      6	- dcr-reg		: < DCR register range >
      7
      8Optional properties:
      9	- er-offset		: All 4xx SoCs with a CPM controller have
     10				  one of two different order for the CPM
     11				  registers. Some have the CPM registers
     12				  in the following order (ER,FR,SR). The
     13				  others have them in the following order
     14				  (SR,ER,FR). For the second case set
     15				  er-offset = <1>.
     16	- unused-units		: specifier consist of one cell. For each
     17				  bit in the cell, the corresponding bit
     18				  in CPM will be set to turn off unused
     19				  devices.
     20	- idle-doze		: specifier consist of one cell. For each
     21				  bit in the cell, the corresponding bit
     22				  in CPM will be set to turn off unused
     23				  devices. This is usually just CPM[CPU].
     24	- standby		: specifier consist of one cell. For each
     25				  bit in the cell, the corresponding bit
     26				  in CPM will be set on standby and
     27				  restored on resume.
     28	- suspend		: specifier consist of one cell. For each
     29				  bit in the cell, the corresponding bit
     30				  in CPM will be set on suspend (mem) and
     31				  restored on resume. Note, for standby
     32				  and suspend the corresponding bits can
     33				  be different or the same. Usually for
     34				  standby only class 2 and 3 units are set.
     35				  However, the interface does not care.
     36				  If they are the same, the additional
     37				  power saving will be seeing if support
     38				  is available to put the DDR in self
     39				  refresh mode and any additional power
     40				  saving techniques for the specific SoC.
     41
     42Example:
     43	CPM0: cpm {
     44		compatible = "ibm,cpm";
     45		dcr-access-method = "native";
     46		dcr-reg = <0x160 0x003>;
     47		er-offset = <0>;
     48		unused-units = <0x00000100>;
     49		idle-doze = <0x02000000>;
     50		standby = <0xfeff0000>;
     51		suspend = <0xfeff791d>;
     52};