cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ppc440spe-adma.txt (2101B)

      1PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
      2
      3Device nodes needed for operation of the ppc440spe-adma driver
      4are specified hereby. These are I2O/DMA, DMA and XOR nodes
      5for DMA engines and Memory Queue Module node. The latter is used
      6by ADMA driver for configuration of RAID-6 H/W capabilities of
      7the PPC440SPe. In addition to the nodes and properties described
      8below, the ranges property of PLB node must specify ranges for
      9DMA devices.
     10
     11 i) The I2O node
     12
     13 Required properties:
     14
     15 - compatible		: "ibm,i2o-440spe";
     16 - reg			: <registers mapping>
     17 - dcr-reg		: <DCR registers range>
     18
     19 Example:
     20
     21	I2O: i2o@400100000 {
     22		compatible = "ibm,i2o-440spe";
     23		reg = <0x00000004 0x00100000 0x100>;
     24		dcr-reg = <0x060 0x020>;
     25	};
     26
     27
     28 ii) The DMA node
     29
     30 Required properties:
     31
     32 - compatible		: "ibm,dma-440spe";
     33 - cell-index		: 1 cell, hardware index of the DMA engine
     34			  (typically 0x0 and 0x1 for DMA0 and DMA1)
     35 - reg			: <registers mapping>
     36 - dcr-reg		: <DCR registers range>
     37 - interrupts		: <interrupt mapping for DMA0/1 interrupts sources:
     38			   2 sources: DMAx CS FIFO Needs Service IRQ (on UIC0)
     39			   and DMA Error IRQ (on UIC1). The latter is common
     40			   for both DMA engines>.
     41
     42 Example:
     43
     44	DMA0: dma0@400100100 {
     45		compatible = "ibm,dma-440spe";
     46		cell-index = <0>;
     47		reg = <0x00000004 0x00100100 0x100>;
     48		dcr-reg = <0x060 0x020>;
     49		interrupt-parent = <&DMA0>;
     50		interrupts = <0 1>;
     51		#interrupt-cells = <1>;
     52		#address-cells = <0>;
     53		#size-cells = <0>;
     54		interrupt-map = <
     55			0 &UIC0 0x14 4
     56			1 &UIC1 0x16 4>;
     57	};
     58
     59
     60 iii) XOR Accelerator node
     61
     62 Required properties:
     63
     64 - compatible		: "amcc,xor-accelerator";
     65 - reg			: <registers mapping>
     66 - interrupts		: <interrupt mapping for XOR interrupt source>
     67
     68 Example:
     69
     70	xor-accel@400200000 {
     71		compatible = "amcc,xor-accelerator";
     72		reg = <0x00000004 0x00200000 0x400>;
     73		interrupt-parent = <&UIC1>;
     74		interrupts = <0x1f 4>;
     75	};
     76
     77
     78 iv) Memory Queue Module node
     79
     80 Required properties:
     81
     82 - compatible		: "ibm,mq-440spe";
     83 - dcr-reg		: <DCR registers range>
     84
     85 Example:
     86
     87	MQ0: mq {
     88		compatible = "ibm,mq-440spe";
     89		dcr-reg = <0x040 0x020>;
     90	};
     91