cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mpc5121-psc.txt (2461B)


      1MPC5121 PSC Device Tree Bindings
      2
      3PSC in UART mode
      4----------------
      5
      6For PSC in UART mode the needed PSC serial devices
      7are specified by fsl,mpc5121-psc-uart nodes in the
      8fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
      9Controller node fsl,mpc5121-psc-fifo is required there:
     10
     11fsl,mpc512x-psc-uart nodes
     12--------------------------
     13
     14Required properties :
     15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
     16   Supported <soc>s: mpc5121, mpc5125
     17 - reg : Offset and length of the register set for the PSC device
     18 - interrupts : <a b> where a is the interrupt number of the
     19   PSC FIFO Controller and b is a field that represents an
     20   encoding of the sense and level information for the interrupt.
     21
     22Recommended properties :
     23 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
     24 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
     25
     26PSC in SPI mode
     27---------------
     28
     29Similar to the UART mode a PSC can be operated in SPI mode. The compatible used
     30for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well.
     31The required and recommended properties are identical to the
     32fsl,mpc5121-psc-uart nodes, just use spi instead of uart in the compatible
     33string.
     34
     35fsl,mpc512x-psc-fifo node
     36-------------------------
     37
     38Required properties :
     39 - compatible : Should be "fsl,<soc>-psc-fifo"
     40   Supported <soc>s: mpc5121, mpc5125
     41 - reg : Offset and length of the register set for the PSC
     42         FIFO Controller
     43 - interrupts : <a b> where a is the interrupt number of the
     44   PSC FIFO Controller and b is a field that represents an
     45   encoding of the sense and level information for the interrupt.
     46
     47Recommended properties :
     48 - clocks : specifies the clock needed to operate the fifo controller
     49 - clock-names : name(s) for the clock(s) listed in clocks
     50
     51Example for a board using PSC0 and PSC1 devices in serial mode:
     52
     53serial@11000 {
     54	compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
     55	cell-index = <0>;
     56	reg = <0x11000 0x100>;
     57	interrupts = <40 0x8>;
     58	interrupt-parent = < &ipic >;
     59	fsl,rx-fifo-size = <16>;
     60	fsl,tx-fifo-size = <16>;
     61};
     62
     63serial@11100 {
     64	compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
     65	cell-index = <1>;
     66	reg = <0x11100 0x100>;
     67	interrupts = <40 0x8>;
     68	interrupt-parent = < &ipic >;
     69	fsl,rx-fifo-size = <16>;
     70	fsl,tx-fifo-size = <16>;
     71};
     72
     73pscfifo@11f00 {
     74	compatible = "fsl,mpc5121-psc-fifo";
     75	reg = <0x11f00 0x100>;
     76	interrupts = <40 0x8>;
     77	interrupt-parent = < &ipic >;
     78};