cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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msi-pic.txt (4483B)


      1* Freescale MSI interrupt controller
      2
      3Required properties:
      4- compatible : compatible list, may contain one or two entries
      5  The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
      6  etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
      7  "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
      8  version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
      9  provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
     10  should be used. The first entry is optional; the second entry is
     11  required.
     12
     13- reg : It may contain one or two regions. The first region should contain
     14  the address and the length of the shared message interrupt register set.
     15  The second region should contain the address of aliased MSIIR or MSIIR1
     16  register for platforms that have such an alias, if using MSIIR1, the second
     17  region must be added because different MSI group has different MSIIR1 offset.
     18
     19- interrupts : each one of the interrupts here is one entry per 32 MSIs,
     20  and routed to the host interrupt controller. the interrupts should
     21  be set as edge sensitive.  If msi-available-ranges is present, only
     22  the interrupts that correspond to available ranges shall be present.
     23
     24Optional properties:
     25- msi-available-ranges: use <start count> style section to define which
     26  msi interrupt can be used in the 256 msi interrupts. This property is
     27  optional, without this, all the MSI interrupts can be used.
     28  Each available range must begin and end on a multiple of 32 (i.e.
     29  no splitting an individual MSI register or the associated PIC interrupt).
     30  MPIC v4.3 does not support this property because the 32 interrupts of an
     31  individual register are not continuous when using MSIIR1.
     32
     33- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
     34  is used for MSI messaging.  The address of MSIIR in PCI address space is
     35  the MSI message address.
     36
     37  This property may be used in virtualized environments where the hypervisor
     38  has created an alternate mapping for the MSIR block.  See below for an
     39  explanation.
     40
     41
     42Example:
     43	msi@41600 {
     44		compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
     45		reg = <0x41600 0x80>;
     46		msi-available-ranges = <0 0x100>;
     47		interrupts = <
     48			0xe0 0
     49			0xe1 0
     50			0xe2 0
     51			0xe3 0
     52			0xe4 0
     53			0xe5 0
     54			0xe6 0
     55			0xe7 0>;
     56		interrupt-parent = <&mpic>;
     57	};
     58
     59	msi@41600 {
     60		compatible = "fsl,mpic-msi-v4.3";
     61		reg = <0x41600 0x200 0x44148 4>;
     62		interrupts = <
     63			0xe0 0 0 0
     64			0xe1 0 0 0
     65			0xe2 0 0 0
     66			0xe3 0 0 0
     67			0xe4 0 0 0
     68			0xe5 0 0 0
     69			0xe6 0 0 0
     70			0xe7 0 0 0
     71			0x100 0 0 0
     72			0x101 0 0 0
     73			0x102 0 0 0
     74			0x103 0 0 0
     75			0x104 0 0 0
     76			0x105 0 0 0
     77			0x106 0 0 0
     78			0x107 0 0 0>;
     79	};
     80
     81The Freescale hypervisor and msi-address-64
     82-------------------------------------------
     83Normally, PCI devices have access to all of CCSR via an ATMU mapping.  The
     84Freescale MSI driver calculates the address of MSIIR (in the MSI register
     85block) and sets that address as the MSI message address.
     86
     87In a virtualized environment, the hypervisor may need to create an IOMMU
     88mapping for MSIIR.  The Freescale ePAPR hypervisor has this requirement
     89because of hardware limitations of the Peripheral Access Management Unit
     90(PAMU), which is currently the only IOMMU that the hypervisor supports.
     91The ATMU is programmed with the guest physical address, and the PAMU
     92intercepts transactions and reroutes them to the true physical address.
     93
     94In the PAMU, each PCI controller is given only one primary window.  The
     95PAMU restricts DMA operations so that they can only occur within a window.
     96Because PCI devices must be able to DMA to memory, the primary window must
     97be used to cover all of the guest's memory space.
     98
     99PAMU primary windows can be divided into 256 subwindows, and each
    100subwindow can have its own address mapping ("guest physical" to "true
    101physical").  However, each subwindow has to have the same alignment, which
    102means they cannot be located at just any address.  Because of these
    103restrictions, it is usually impossible to create a 4KB subwindow that
    104covers MSIIR where it's normally located.
    105
    106Therefore, the hypervisor has to create a subwindow inside the same
    107primary window used for memory, but mapped to the MSIR block (where MSIIR
    108lives).  The first subwindow after the end of guest memory is used for
    109this.  The address specified in the msi-address-64 property is the PCI
    110address of MSIIR.  The hypervisor configures the PAMU to map that address to
    111the true physical address of MSIIR.