cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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srio.txt (3418B)


      1* Freescale Serial RapidIO (SRIO) Controller
      2
      3RapidIO port node:
      4Properties:
      5   - compatible
      6	Usage: required
      7	Value type: <string>
      8	Definition: Must include "fsl,srio" for IP blocks with IP Block
      9	Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
     10
     11	Optionally, a compatible string of "fsl,srio-vX.Y" where X is Major
     12	version in IP Block Revision Register and Y is Minor version.  If this
     13	compatible is provided it should be ordered before "fsl,srio".
     14
     15   - reg
     16	Usage: required
     17	Value type: <prop-encoded-array>
     18	Definition: A standard property.  Specifies the physical address and
     19		length of the SRIO configuration registers.  The size should
     20		be set to 0x11000.
     21
     22   - interrupts
     23	Usage: required
     24	Value type: <prop_encoded-array>
     25	Definition:  Specifies the interrupts generated by this device.  The
     26		value of the interrupts property consists of one interrupt
     27		specifier. The format of the specifier is defined by the
     28		binding document describing the node's interrupt parent.
     29
     30		A single IRQ that handles error conditions is specified by this
     31		property.  (Typically shared with port-write).
     32
     33   - fsl,srio-rmu-handle:
     34	Usage: required if rmu node is defined
     35	Value type: <phandle>
     36	Definition: A single <phandle> value that points to the RMU.
     37	(See srio-rmu.txt for more details on RMU node binding)
     38
     39Port Child Nodes:  There should a port child node for each port that exists in
     40the controller.  The ports are numbered starting at one (1) and should have
     41the following properties:
     42
     43   - cell-index
     44	Usage: required
     45	Value type: <u32>
     46	Definition: A standard property.  Matches the port id.
     47
     48   - ranges
     49	Usage: required if local access windows preset
     50	Value type: <prop-encoded-array>
     51	Definition: A standard property. Utilized to describe the memory mapped
     52		IO space utilized by the controller.  This corresponds to the
     53		setting of the local access windows that are targeted to this
     54		SRIO port.
     55
     56   - fsl,liodn
     57	Usage: optional-but-recommended (for devices with PAMU)
     58	Value type: <prop-encoded-array>
     59	Definition: The logical I/O device number for the PAMU (IOMMU) to be
     60		correctly configured for SRIO accesses.  The property should
     61		not exist on devices that do not support PAMU.
     62
     63		For HW (ie, the P4080) that only supports a LIODN for both
     64		memory and maintenance transactions then a single LIODN is
     65		represented in the property for both transactions.
     66
     67		For HW (ie, the P304x/P5020, etc) that supports an LIODN for
     68		memory transactions and a unique LIODN for maintenance
     69		transactions then a pair of LIODNs are represented in the
     70		property.  Within the pair, the first element represents the
     71		LIODN associated with memory transactions and the second element
     72		represents the LIODN associated with maintenance transactions
     73		for the port.
     74
     75Note: All other standard properties (see the Devicetree Specification)
     76are allowed but are optional.
     77
     78Example:
     79
     80	rapidio: rapidio@ffe0c0000 {
     81		#address-cells = <2>;
     82		#size-cells = <2>;
     83		reg = <0xf 0xfe0c0000 0 0x11000>;
     84		compatible = "fsl,srio";
     85		interrupts = <16 2 1 11>; /* err_irq */
     86		fsl,srio-rmu-handle = <&rmu>;
     87		ranges;
     88
     89		port1 {
     90			cell-index = <1>;
     91			#address-cells = <2>;
     92			#size-cells = <2>;
     93			fsl,liodn = <34>;
     94			ranges = <0 0 0xc 0x20000000 0 0x10000000>;
     95		};
     96
     97		port2 {
     98			cell-index = <2>;
     99			#address-cells = <2>;
    100			#size-cells = <2>;
    101			fsl,liodn = <48>;
    102			ranges = <0 0 0xc 0x30000000 0 0x10000000>;
    103		};
    104	};