pwm-mediatek.txt (1913B)
1MediaTek PWM controller 2 3Required properties: 4 - compatible: should be "mediatek,<name>-pwm": 5 - "mediatek,mt2712-pwm": found on mt2712 SoC. 6 - "mediatek,mt6795-pwm": found on mt6795 SoC. 7 - "mediatek,mt7622-pwm": found on mt7622 SoC. 8 - "mediatek,mt7623-pwm": found on mt7623 SoC. 9 - "mediatek,mt7628-pwm": found on mt7628 SoC. 10 - "mediatek,mt7629-pwm": found on mt7629 SoC. 11 - "mediatek,mt8183-pwm": found on mt8183 SoC. 12 - "mediatek,mt8516-pwm": found on mt8516 SoC. 13 - reg: physical base address and length of the controller's registers. 14 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of 15 the cell format. 16 - clocks: phandle and clock specifier of the PWM reference clock. 17 - clock-names: must contain the following, except for MT7628 which 18 has no clocks 19 - "top": the top clock generator 20 - "main": clock used by the PWM core 21 - "pwm1-8": the eight per PWM clocks for mt2712 22 - "pwm1-6": the six per PWM clocks for mt7622 23 - "pwm1-5": the five per PWM clocks for mt7623 24 - "pwm1" : the PWM1 clock for mt7629 25 - pinctrl-names: Must contain a "default" entry. 26 - pinctrl-0: One property must exist for each entry in pinctrl-names. 27 See pinctrl/pinctrl-bindings.txt for details of the property values. 28 29Optional properties: 30- assigned-clocks: Reference to the PWM clock entries. 31- assigned-clock-parents: The phandle of the parent clock of PWM clock. 32 33Example: 34 pwm0: pwm@11006000 { 35 compatible = "mediatek,mt7623-pwm"; 36 reg = <0 0x11006000 0 0x1000>; 37 #pwm-cells = <2>; 38 clocks = <&topckgen CLK_TOP_PWM_SEL>, 39 <&pericfg CLK_PERI_PWM>, 40 <&pericfg CLK_PERI_PWM1>, 41 <&pericfg CLK_PERI_PWM2>, 42 <&pericfg CLK_PERI_PWM3>, 43 <&pericfg CLK_PERI_PWM4>, 44 <&pericfg CLK_PERI_PWM5>; 45 clock-names = "top", "main", "pwm1", "pwm2", 46 "pwm3", "pwm4", "pwm5"; 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pwm0_pins>; 49 };