socionext,uniphier-regulator.yaml (2386B)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/regulator/socionext,uniphier-regulator.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Socionext UniPhier regulator controller 8 9description: | 10 This regulator controls VBUS and belongs to USB3 glue layer. Before using 11 the regulator, it is necessary to control the clocks and resets to enable 12 this layer. These clocks and resets should be described in each property. 13 14maintainers: 15 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 16 17# USB3 Controller 18 19properties: 20 compatible: 21 enum: 22 - socionext,uniphier-pro4-usb3-regulator 23 - socionext,uniphier-pro5-usb3-regulator 24 - socionext,uniphier-pxs2-usb3-regulator 25 - socionext,uniphier-ld20-usb3-regulator 26 - socionext,uniphier-pxs3-usb3-regulator 27 - socionext,uniphier-nx1-usb3-regulator 28 29 reg: 30 maxItems: 1 31 32 clocks: 33 minItems: 1 34 maxItems: 2 35 36 clock-names: true 37 38 resets: 39 minItems: 1 40 maxItems: 2 41 42 reset-names: true 43 44allOf: 45 - $ref: "regulator.yaml#" 46 - if: 47 properties: 48 compatible: 49 contains: 50 enum: 51 - socionext,uniphier-pro4-usb3-regulator 52 - socionext,uniphier-pro5-usb3-regulator 53 then: 54 properties: 55 clocks: 56 minItems: 2 57 maxItems: 2 58 clock-names: 59 items: 60 - const: gio 61 - const: link 62 resets: 63 minItems: 2 64 maxItems: 2 65 reset-names: 66 items: 67 - const: gio 68 - const: link 69 else: 70 properties: 71 clocks: 72 maxItems: 1 73 clock-names: 74 const: link 75 resets: 76 maxItems: 1 77 reset-names: 78 const: link 79 80unevaluatedProperties: false 81 82required: 83 - compatible 84 - reg 85 - clocks 86 - clock-names 87 - resets 88 - reset-names 89 90examples: 91 - | 92 usb-glue@65b00000 { 93 compatible = "simple-mfd"; 94 #address-cells = <1>; 95 #size-cells = <1>; 96 ranges = <0 0x65b00000 0x400>; 97 98 usb_vbus0: regulators@100 { 99 compatible = "socionext,uniphier-ld20-usb3-regulator"; 100 reg = <0x100 0x10>; 101 clock-names = "link"; 102 clocks = <&sys_clk 14>; 103 reset-names = "link"; 104 resets = <&sys_rst 14>; 105 }; 106 };