cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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ti-abb-regulator.txt (5520B)


      1Adaptive Body Bias(ABB) SoC internal LDO regulator for Texas Instruments SoCs
      2
      3Required Properties:
      4- compatible: Should be one of:
      5  - "ti,abb-v1" for older SoCs like OMAP3
      6  - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
      7  - "ti,abb-v3" for a generic definition where setup and control registers are
      8     provided (example: DRA7)
      9- reg: Address and length of the register set for the device. It contains
     10  the information of registers in the same order as described by reg-names
     11- reg-names: Should contain the reg names
     12  - "base-address"	- contains base address of ABB module (ti,abb-v1,ti,abb-v2)
     13  - "control-address"	- contains control register address of ABB module (ti,abb-v3)
     14  - "setup-address"	- contains setup register address of ABB module (ti,abb-v3)
     15  - "int-address"	- contains address of interrupt register for ABB module
     16  (also see Optional properties)
     17- #address-cells: should be 0
     18- #size-cells: should be 0
     19- clocks: should point to the clock node used by ABB module
     20- ti,settling-time: Settling time in uSecs from SoC documentation for ABB module
     21	to settle down(target time for SR2_WTCNT_VALUE).
     22- ti,clock-cycles: SoC specific data about count of system ti,clock-cycles used for
     23	computing settling time from SoC Documentation for ABB module(clock
     24	cycles for SR2_WTCNT_VALUE).
     25- ti,tranxdone-status-mask: Mask to the int-register to write-to-clear mask
     26	indicating LDO tranxdone (operation complete).
     27- ti,abb_info: An array of 6-tuples u32 items providing information about ABB
     28	configuration needed per operational voltage of the device.
     29	Each item consists of the following in the same order:
     30	volt: voltage in uV - Only used to index ABB information.
     31	ABB mode: one of the following:
     32		0-bypass
     33		1-Forward Body Bias(FBB)
     34		3-Reverse Body Bias(RBB)
     35	efuse:	(see Optional properties)
     36	RBB enable efuse Mask:	(See Optional properties)
     37	FBB enable efuse Mask:	(See Optional properties)
     38	Vset value efuse Mask:	(See Optional properties)
     39
     40	NOTE: If more than 1 entry is present, then regulator is setup to change
     41	      voltage, allowing for various modes to be selected indexed off
     42	      the regulator. Further, ABB LDOs are considered always-on by
     43	      default.
     44
     45Optional Properties:
     46- reg-names: In addition to the required properties, the following are optional
     47  - "efuse-address"	- Contains efuse base address used to pick up ABB info.
     48  - "ldo-address"	- Contains address of ABB LDO override register.
     49	"efuse-address" is required for this.
     50- ti,ldovbb-vset-mask	- Required if ldo-address is set, mask for LDO override
     51	register to provide override vset value.
     52- ti,ldovbb-override-mask - Required if ldo-address is set, mask for LDO
     53	override register to enable override vset value.
     54- ti,abb_opp_sel: Addendum to the description in required properties
     55	efuse: Mandatory if 'efuse-address' register is defined. Provides offset
     56	       from efuse-address to pick up ABB characteristics. Set to 0 if
     57	       'efuse-address' is not defined.
     58	RBB enable efuse Mask:	Optional if 'efuse-address' register is defined.
     59		'ABB mode' is force set to RBB mode if value at "efuse-address"
     60		+ efuse maps to RBB mask. Set to 0 to ignore this.
     61	FBB enable efuse Mask:	Optional if 'efuse-address' register is defined.
     62		'ABB mode' is force set to FBB mode if value at "efuse-address"
     63		+ efuse maps to FBB mask (valid only if RBB mask does not match)
     64		Set to 0 to ignore this.
     65	Vset value efuse Mask:	Mandatory if ldo-address is set. Picks up from
     66		efuse the value to set in 'ti,ldovbb-vset-mask' at ldo-address.
     67
     68Example #1: Simplest configuration (no efuse data, hard coded ABB table):
     69abb_x: regulator-abb-x {
     70	compatible = "ti,abb-v1";
     71	regulator-name = "abb_x";
     72	#address-cells = <0>;
     73	#size-cells = <0>;
     74	reg = <0x483072f0 0x8>, <0x48306818 0x4>;
     75	reg-names = "base-address", "int-address";
     76	ti,tranxdone-status-mask = <0x4000000>;
     77	clocks = <&sysclk>;
     78	ti,settling-time = <30>;
     79	ti,clock-cycles = <8>;
     80	ti,abb_info = <
     81	/* uV		ABB	efuse	rbb_m	fbb_m	vset_m */
     82	1012500		0	0	0	0	0 /* Bypass */
     83	1200000		3	0	0	0	0 /* RBB mandatory */
     84	1320000		1	0	0	0	0 /* FBB mandatory */
     85	>;
     86};
     87
     88Example #2: Efuse bits contain ABB mode setting (no LDO override capability)
     89abb_y: regulator-abb-y {
     90	compatible = "ti,abb-v2";
     91	regulator-name = "abb_y";
     92	#address-cells = <0>;
     93	#size-cells = <0>;
     94	reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, <0x4A002268 0x8>;
     95	reg-names = "base-address", "int-address", "efuse-address";
     96	ti,tranxdone-status-mask = <0x4000000>;
     97	clocks = <&sysclk>;
     98	ti,settling-time = <50>;
     99	ti,clock-cycles = <16>;
    100	ti,abb_info = <
    101	/* uV		ABB	efuse	rbb_m	fbb_m	vset_m */
    102	975000		0	0	0	0	0 /* Bypass */
    103	1012500		0	0	0x40000	0	0 /* RBB optional */
    104	1200000		0	0x4	0	0x40000	0 /* FBB optional */
    105	1320000		1	0	0	0	0 /* FBB mandatory */
    106	>;
    107};
    108
    109Example #3: Efuse bits contain ABB mode setting and LDO override capability
    110abb_z: regulator-abb-z {
    111	compatible = "ti,abb-v2";
    112	regulator-name = "abb_z";
    113	#address-cells = <0>;
    114	#size-cells = <0>;
    115	reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
    116	      <0x4a002194 0x8>, <0x4ae0C314 0x4>;
    117	reg-names = "base-address", "int-address",
    118		    "efuse-address", "ldo-address";
    119	ti,tranxdone-status-mask = <0x8000000>;
    120	/* LDOVBBMM_MUX_CTRL */
    121	ti,ldovbb-override-mask = <0x400>;
    122	/* LDOVBBMM_VSET_OUT */
    123	ti,ldovbb-vset-mask = <0x1F>;
    124	clocks = <&sysclk>;
    125	ti,settling-time = <50>;
    126	ti,clock-cycles = <16>;
    127	ti,abb_info = <
    128	/* uV	ABB	efuse	rbb_m	fbb_m	vset_m */
    129	975000	0	0	0	0	0	/* Bypass */
    130	1200000	0	0x4	0	0x40000	0x1f00	/* FBB optional, vset */
    131	>;
    132};