cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,qcs404-cdsp-pil.yaml (4353B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-cdsp-pil.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm QCS404 CDSP Peripheral Image Loader
      8
      9maintainers:
     10  - Bjorn Andersson <bjorn.andersson@linaro.org>
     11
     12description:
     13  This document defines the binding for a component that loads and boots firmware
     14  on the Qualcomm Technology Inc. CDSP (Compute DSP).
     15
     16properties:
     17  compatible:
     18    enum:
     19      - qcom,qcs404-cdsp-pil
     20
     21  reg:
     22    maxItems: 1
     23    description:
     24      The base address and size of the qdsp6ss register
     25
     26  interrupts:
     27    items:
     28      - description: Watchdog interrupt
     29      - description: Fatal interrupt
     30      - description: Ready interrupt
     31      - description: Handover interrupt
     32      - description: Stop acknowledge interrupt
     33
     34  interrupt-names:
     35    items:
     36      - const: wdog
     37      - const: fatal
     38      - const: ready
     39      - const: handover
     40      - const: stop-ack
     41
     42  clocks:
     43    items:
     44      - description: XO clock
     45      - description: SWAY clock
     46      - description: TBU clock
     47      - description: BIMC clock
     48      - description: AHB AON clock
     49      - description: Q6SS SLAVE clock
     50      - description: Q6SS MASTER clock
     51      - description: Q6 AXIM clock
     52
     53  clock-names:
     54    items:
     55      - const: xo
     56      - const: sway
     57      - const: tbu
     58      - const: bimc
     59      - const: ahb_aon
     60      - const: q6ss_slave
     61      - const: q6ss_master
     62      - const: q6_axim
     63
     64  power-domains:
     65    items:
     66      - description: CX power domain
     67
     68  resets:
     69    items:
     70      - description: AOSS restart
     71
     72  reset-names:
     73    items:
     74      - const: restart
     75
     76  memory-region:
     77    maxItems: 1
     78    description: Reference to the reserved-memory for the Hexagon core
     79
     80  qcom,halt-regs:
     81    $ref: /schemas/types.yaml#/definitions/phandle-array
     82    description:
     83      Phandle reference to a syscon representing TCSR followed by the
     84      three offsets within syscon for q6, modem and nc halt registers.
     85
     86  qcom,smem-states:
     87    $ref: /schemas/types.yaml#/definitions/phandle-array
     88    description: States used by the AP to signal the Hexagon core
     89    items:
     90      - description: Stop the modem
     91
     92  qcom,smem-state-names:
     93    $ref: /schemas/types.yaml#/definitions/string
     94    description: The names of the state bits used for SMP2P output
     95    items:
     96      - const: stop
     97
     98required:
     99  - compatible
    100  - reg
    101  - interrupts
    102  - interrupt-names
    103  - clocks
    104  - clock-names
    105  - power-domains
    106  - resets
    107  - reset-names
    108  - qcom,halt-regs
    109  - memory-region
    110  - qcom,smem-states
    111  - qcom,smem-state-names
    112
    113additionalProperties: false
    114
    115examples:
    116  - |
    117    #include <dt-bindings/interrupt-controller/arm-gic.h>
    118    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
    119    #include <dt-bindings/power/qcom-rpmpd.h>
    120    #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
    121    remoteproc@b00000 {
    122        compatible = "qcom,qcs404-cdsp-pil";
    123        reg = <0x00b00000 0x4040>;
    124
    125        interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
    126                              <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
    127                              <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
    128                              <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
    129                              <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
    130        interrupt-names = "wdog", "fatal", "ready",
    131                          "handover", "stop-ack";
    132
    133        clocks = <&xo_board>,
    134                 <&gcc GCC_CDSP_CFG_AHB_CLK>,
    135                 <&gcc GCC_CDSP_TBU_CLK>,
    136                 <&gcc GCC_BIMC_CDSP_CLK>,
    137                 <&turingcc TURING_WRAPPER_AON_CLK>,
    138                 <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
    139                 <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
    140                 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
    141        clock-names = "xo",
    142                      "sway",
    143                      "tbu",
    144                      "bimc",
    145                      "ahb_aon",
    146                      "q6ss_slave",
    147                      "q6ss_master",
    148                      "q6_axim";
    149
    150        power-domains = <&rpmhpd SDM845_CX>;
    151
    152        resets = <&gcc GCC_CDSP_RESTART>;
    153        reset-names = "restart";
    154
    155        qcom,halt-regs = <&tcsr 0x19004>;
    156
    157        memory-region = <&cdsp_fw_mem>;
    158
    159        qcom,smem-states = <&cdsp_smp2p_out 0>;
    160        qcom,smem-state-names = "stop";
    161    };