cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,sdm845-adsp-pil.yaml (4483B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/remoteproc/qcom,sdm845-adsp-pil.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm SDM845 ADSP Peripheral Image Loader
      8
      9maintainers:
     10  - Bjorn Andersson <bjorn.andersson@linaro.org>
     11
     12description:
     13  This document defines the binding for a component that loads and boots firmware
     14  on the Qualcomm Technology Inc. ADSP.
     15
     16properties:
     17  compatible:
     18    enum:
     19      - qcom,sdm845-adsp-pil
     20
     21  reg:
     22    maxItems: 1
     23    description:
     24      The base address and size of the qdsp6ss register
     25
     26  interrupts:
     27    items:
     28      - description: Watchdog interrupt
     29      - description: Fatal interrupt
     30      - description: Ready interrupt
     31      - description: Handover interrupt
     32      - description: Stop acknowledge interrupt
     33
     34  interrupt-names:
     35    items:
     36      - const: wdog
     37      - const: fatal
     38      - const: ready
     39      - const: handover
     40      - const: stop-ack
     41
     42  clocks:
     43    items:
     44      - description: XO clock
     45      - description: SWAY clock
     46      - description: LPASS AHBS AON clock
     47      - description: LPASS AHBM AON clock
     48      - description: QDSP XO clock
     49      - description: Q6SP6SS SLEEP clock
     50      - description: Q6SP6SS CORE clock
     51
     52  clock-names:
     53    items:
     54      - const: xo
     55      - const: sway_cbcr
     56      - const: lpass_ahbs_aon_cbcr
     57      - const: lpass_ahbm_aon_cbcr
     58      - const: qdsp6ss_xo
     59      - const: qdsp6ss_sleep
     60      - const: qdsp6ss_core
     61
     62  power-domains:
     63    items:
     64      - description: CX power domain
     65
     66  resets:
     67    items:
     68      - description: PDC AUDIO SYNC RESET
     69      - description: CC LPASS restart
     70
     71  reset-names:
     72    items:
     73      - const: pdc_sync
     74      - const: cc_lpass
     75
     76  memory-region:
     77    maxItems: 1
     78    description: Reference to the reserved-memory for the Hexagon core
     79
     80  qcom,halt-regs:
     81    $ref: /schemas/types.yaml#/definitions/phandle-array
     82    description:
     83      Phandle reference to a syscon representing TCSR followed by the
     84      three offsets within syscon for q6, modem and nc halt registers.
     85
     86  qcom,smem-states:
     87    $ref: /schemas/types.yaml#/definitions/phandle-array
     88    description: States used by the AP to signal the Hexagon core
     89    items:
     90      - description: Stop the modem
     91
     92  qcom,smem-state-names:
     93    $ref: /schemas/types.yaml#/definitions/string
     94    description: The names of the state bits used for SMP2P output
     95    items:
     96      - const: stop
     97
     98required:
     99  - compatible
    100  - reg
    101  - interrupts
    102  - interrupt-names
    103  - clocks
    104  - clock-names
    105  - power-domains
    106  - resets
    107  - reset-names
    108  - qcom,halt-regs
    109  - memory-region
    110  - qcom,smem-states
    111  - qcom,smem-state-names
    112
    113additionalProperties: false
    114
    115examples:
    116  - |
    117    #include <dt-bindings/interrupt-controller/arm-gic.h>
    118    #include <dt-bindings/clock/qcom,rpmh.h>
    119    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    120    #include <dt-bindings/clock/qcom,lpass-sdm845.h>
    121    #include <dt-bindings/power/qcom-rpmpd.h>
    122    #include <dt-bindings/reset/qcom,sdm845-pdc.h>
    123    #include <dt-bindings/reset/qcom,sdm845-aoss.h>
    124    remoteproc@17300000 {
    125        compatible = "qcom,sdm845-adsp-pil";
    126        reg = <0x17300000 0x40c>;
    127
    128        interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
    129                <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
    130                <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
    131                <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
    132                <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
    133        interrupt-names = "wdog", "fatal", "ready",
    134                "handover", "stop-ack";
    135
    136        clocks = <&rpmhcc RPMH_CXO_CLK>,
    137                 <&gcc GCC_LPASS_SWAY_CLK>,
    138                 <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
    139                 <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
    140                 <&lpasscc LPASS_QDSP6SS_XO_CLK>,
    141                 <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
    142                 <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
    143        clock-names = "xo", "sway_cbcr",
    144                "lpass_ahbs_aon_cbcr",
    145                "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
    146                "qdsp6ss_sleep", "qdsp6ss_core";
    147
    148        power-domains = <&rpmhpd SDM845_CX>;
    149
    150        resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
    151                 <&aoss_reset AOSS_CC_LPASS_RESTART>;
    152        reset-names = "pdc_sync", "cc_lpass";
    153
    154        qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
    155
    156        memory-region = <&pil_adsp_mem>;
    157
    158        qcom,smem-states = <&adsp_smp2p_out 0>;
    159        qcom,smem-state-names = "stop";
    160    };