cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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amlogic,meson-axg-audio-arb.yaml (1256B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2# Copyright 2019 BayLibre, SAS
      3%YAML 1.2
      4---
      5$id: "http://devicetree.org/schemas/reset/amlogic,meson-axg-audio-arb.yaml#"
      6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      7
      8title: Amlogic audio memory arbiter controller
      9
     10maintainers:
     11  - Jerome Brunet <jbrunet@baylibre.com>
     12
     13description: The Amlogic Audio ARB is a simple device which enables or disables
     14  the access of Audio FIFOs to DDR on AXG based SoC.
     15
     16properties:
     17  compatible:
     18    enum:
     19      - amlogic,meson-axg-audio-arb
     20      - amlogic,meson-sm1-audio-arb
     21
     22  reg:
     23    maxItems: 1
     24
     25  clocks:
     26    maxItems: 1
     27    description: |
     28      phandle to the fifo peripheral clock provided by the audio clock
     29      controller.
     30
     31  "#reset-cells":
     32    const: 1
     33
     34required:
     35  - compatible
     36  - reg
     37  - clocks
     38  - "#reset-cells"
     39
     40additionalProperties: false
     41
     42examples:
     43  - |
     44    // on the A113 SoC:
     45    #include <dt-bindings/clock/axg-audio-clkc.h>
     46    bus {
     47        #address-cells = <2>;
     48        #size-cells = <2>;
     49
     50        arb: reset-controller@280 {
     51            compatible = "amlogic,meson-axg-audio-arb";
     52            reg = <0x0 0x280 0x0 0x4>;
     53            #reset-cells = <1>;
     54            clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
     55        };
     56    };