cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

brcm,brcmstb-reset.yaml (1015B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: Broadcom STB SW_INIT-style reset controller
      8
      9description:
     10  Broadcom STB SoCs have a SW_INIT-style reset controller with separate
     11  SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit
     12  reset lines.
     13
     14  Please also refer to reset.txt in this directory for common reset
     15  controller binding usage.
     16
     17maintainers:
     18  - Florian Fainelli <f.fainelli@gmail.com>
     19
     20properties:
     21  compatible:
     22    const: brcm,brcmstb-reset
     23
     24  reg:
     25    maxItems: 1
     26
     27  "#reset-cells":
     28    const: 1
     29
     30required:
     31  - compatible
     32  - reg
     33  - "#reset-cells"
     34
     35additionalProperties: false
     36
     37examples:
     38  - |
     39    reset: reset-controller@8404318 {
     40      compatible = "brcm,brcmstb-reset";
     41      reg = <0x8404318 0x30>;
     42      #reset-cells = <1>;
     43    };
     44
     45    ethernet_switch {
     46      resets = <&reset 26>;
     47      reset-names = "switch";
     48    };