cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,imx7-src.yaml (1560B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Freescale i.MX7 System Reset Controller
      8
      9maintainers:
     10  - Andrey Smirnov <andrew.smirnov@gmail.com>
     11
     12description: |
     13  The system reset controller can be used to reset various set of
     14  peripherals. Device nodes that need access to reset lines should
     15  specify them as a reset phandle in their corresponding node as
     16  specified in reset.txt.
     17
     18  For list of all valid reset indices see
     19    <dt-bindings/reset/imx7-reset.h> for i.MX7,
     20    <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,
     21    <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP.
     22
     23properties:
     24  compatible:
     25    oneOf:
     26      - items:
     27          - enum:
     28              - fsl,imx7d-src
     29              - fsl,imx8mq-src
     30              - fsl,imx8mp-src
     31          - const: syscon
     32      - items:
     33          - enum:
     34              - fsl,imx8mm-src
     35              - fsl,imx8mn-src
     36          - const: fsl,imx8mq-src
     37          - const: syscon
     38
     39  reg:
     40    maxItems: 1
     41
     42  interrupts:
     43    maxItems: 1
     44
     45  '#reset-cells':
     46    const: 1
     47
     48required:
     49  - compatible
     50  - reg
     51  - interrupts
     52  - '#reset-cells'
     53
     54additionalProperties: false
     55
     56examples:
     57  - |
     58    #include <dt-bindings/interrupt-controller/arm-gic.h>
     59
     60    reset-controller@30390000 {
     61        compatible = "fsl,imx7d-src", "syscon";
     62        reg = <0x30390000 0x2000>;
     63        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
     64        #reset-cells = <1>;
     65    };