cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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lantiq,reset.yaml (1184B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/reset/lantiq,reset.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Lantiq XWAY SoC RCU reset controller
      8
      9maintainers:
     10  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
     11
     12description: |
     13  This binding describes a reset-controller found on the RCU module on Lantiq
     14  XWAY SoCs. This node has to be a sub node of the Lantiq RCU block.
     15
     16properties:
     17  compatible:
     18    enum:
     19      - lantiq,danube-reset
     20      - lantiq,xrx200-reset
     21
     22  reg:
     23    description: |
     24      Defines the following sets of registers in the parent syscon device
     25      Offset of the reset set register
     26      Offset of the reset status register
     27    maxItems: 2
     28
     29  '#reset-cells':
     30    description: |
     31      The first cell takes the reset set bit and the second cell takes the
     32      status bit.
     33    const: 2
     34
     35required:
     36  - compatible
     37  - reg
     38  - '#reset-cells'
     39
     40additionalProperties: false
     41
     42examples:
     43  - |
     44    // On the xRX200 SoCs:
     45    reset0: reset-controller@10 {
     46        compatible = "lantiq,xrx200-reset";
     47        reg = <0x10 0x04>, <0x14 0x04>;
     48        #reset-cells = <2>;
     49    };