cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

qcom,aoss-reset.yaml (1256B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/reset/qcom,aoss-reset.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm AOSS Reset Controller
      8
      9maintainers:
     10  - Sibi Sankar <quic_sibis@quicinc.com>
     11
     12description:
     13  The bindings describe the reset-controller found on AOSS-CC (always on
     14  subsystem) for Qualcomm Technologies Inc SoCs.
     15
     16properties:
     17  compatible:
     18    oneOf:
     19      - description: on SC7180 SoCs the following compatibles must be specified
     20        items:
     21          - const: "qcom,sc7180-aoss-cc"
     22          - const: "qcom,sdm845-aoss-cc"
     23
     24      - description: on SC7280 SoCs the following compatibles must be specified
     25        items:
     26          - const: "qcom,sc7280-aoss-cc"
     27          - const: "qcom,sdm845-aoss-cc"
     28
     29      - description: on SDM845 SoCs the following compatibles must be specified
     30        items:
     31          - const: "qcom,sdm845-aoss-cc"
     32
     33  reg:
     34    maxItems: 1
     35
     36  '#reset-cells':
     37    const: 1
     38
     39required:
     40  - compatible
     41  - reg
     42  - '#reset-cells'
     43
     44additionalProperties: false
     45
     46examples:
     47  - |
     48    aoss_reset: reset-controller@c2a0000 {
     49      compatible = "qcom,sdm845-aoss-cc";
     50      reg = <0xc2a0000 0x31000>;
     51      #reset-cells = <1>;
     52    };