cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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renesas,rzg2l-usbphy-ctrl.yaml (1449B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Renesas RZ/{G2L,V2L} USBPHY Control
      8
      9maintainers:
     10  - Biju Das <biju.das.jz@bp.renesas.com>
     11
     12description:
     13  The RZ/G2L USBPHY Control mainly controls reset and power down of the
     14  USB/PHY.
     15
     16properties:
     17  compatible:
     18    items:
     19      - enum:
     20          - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
     21          - renesas,r9a07g054-usbphy-ctrl # RZ/V2L
     22      - const: renesas,rzg2l-usbphy-ctrl
     23
     24  reg:
     25    maxItems: 1
     26
     27  clocks:
     28    maxItems: 1
     29
     30  resets:
     31    maxItems: 1
     32
     33  power-domains:
     34    maxItems: 1
     35
     36  '#reset-cells':
     37    const: 1
     38    description: |
     39      The phandle's argument in the reset specifier is the PHY reset associated
     40      with the USB port.
     41      0 = Port 1 Phy reset
     42      1 = Port 2 Phy reset
     43
     44required:
     45  - compatible
     46  - reg
     47  - clocks
     48  - resets
     49  - power-domains
     50  - '#reset-cells'
     51
     52additionalProperties: false
     53
     54examples:
     55  - |
     56    #include <dt-bindings/clock/r9a07g044-cpg.h>
     57
     58    phyrst: usbphy-ctrl@11c40000 {
     59        compatible = "renesas,r9a07g044-usbphy-ctrl",
     60                     "renesas,rzg2l-usbphy-ctrl";
     61        reg = <0x11c40000 0x10000>;
     62        clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
     63        resets = <&cpg R9A07G044_USB_PRESETN>;
     64        power-domains = <&cpg>;
     65        #reset-cells = <1>;
     66    };