cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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st,stih407-picophyreset.yaml (1325B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/reset/st,stih407-picophyreset.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: STMicroelectronics STi family Sysconfig Picophy SoftReset Controller
      8
      9maintainers:
     10  - Peter Griffin <peter.griffin@linaro.org>
     11
     12description: |
     13  This binding describes a reset controller device that is used to enable and
     14  disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
     15  the STi family SoC system configuration registers.
     16
     17  The actual action taken when softreset is asserted is hardware dependent.
     18  However, when asserted it may not be possible to access the hardware's
     19  registers and after an assert/deassert sequence the hardware's previous state
     20  may no longer be valid.
     21
     22properties:
     23  compatible:
     24    const: st,stih407-picophyreset
     25
     26  '#reset-cells':
     27    const: 1
     28
     29required:
     30  - compatible
     31  - '#reset-cells'
     32
     33additionalProperties: false
     34
     35examples:
     36  - |
     37    #include <dt-bindings/reset/stih407-resets.h>
     38
     39    picophyreset: picophyreset-controller {
     40        compatible = "st,stih407-picophyreset";
     41        #reset-cells = <1>;
     42    };
     43
     44    // Specifying picophyreset control of devices
     45    usb2_picophy0: usbpicophy {
     46        resets = <&picophyreset STIH407_PICOPHY0_RESET>;
     47    };