cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,sci-reset.yaml (1576B)

      1# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: TI-SCI reset controller node bindings
      8
      9maintainers:
     10  - Nishanth Menon <nm@ti.com>
     11
     12description: |
     13  Some TI SoCs contain a system controller (like the Power Management Micro
     14  Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
     15  the state of the various hardware modules present on the SoC. Communication
     16  between the host processor running an OS and the system controller happens
     17  through a protocol called TI System Control Interface (TI-SCI protocol).
     18
     19  This reset controller node uses the TI SCI protocol to perform the reset
     20  management of various hardware modules present on the SoC. Must be a child
     21  node of the associated TI-SCI system controller node.
     22
     23properties:
     24  $nodename:
     25    pattern: "^reset-controller$"
     26
     27  compatible:
     28    const: ti,sci-reset
     29
     30  "#reset-cells":
     31    const: 2
     32    description:
     33      The two cells represent values that the TI-SCI controller defines.
     34
     35      The first cell should contain the device ID.
     36
     37      The second cell should contain the reset mask corresponding to the device
     38      used by system controller.
     39
     40      Please see  http://processors.wiki.ti.com/index.php/TISCI for
     41      protocol documentation for the values to be used for different devices.
     42
     43
     44additionalProperties: false
     45
     46examples:
     47  - |
     48    k3_reset: reset-controller {
     49        compatible = "ti,sci-reset";
     50        #reset-cells = <2>;
     51    };