cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sifive-l2-cache.yaml (2698B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2# Copyright (C) 2020 SiFive, Inc.
      3%YAML 1.2
      4---
      5$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
      6$schema: http://devicetree.org/meta-schemas/core.yaml#
      7
      8title: SiFive L2 Cache Controller
      9
     10maintainers:
     11  - Sagar Kadam <sagar.kadam@sifive.com>
     12  - Paul Walmsley  <paul.walmsley@sifive.com>
     13
     14description:
     15  The SiFive Level 2 Cache Controller is used to provide access to fast copies
     16  of memory for masters in a Core Complex. The Level 2 Cache Controller also
     17  acts as directory-based coherency manager.
     18  All the properties in ePAPR/DeviceTree specification applies for this platform.
     19
     20allOf:
     21  - $ref: /schemas/cache-controller.yaml#
     22
     23select:
     24  properties:
     25    compatible:
     26      contains:
     27        enum:
     28          - sifive,fu540-c000-ccache
     29          - sifive,fu740-c000-ccache
     30
     31  required:
     32    - compatible
     33
     34properties:
     35  compatible:
     36    items:
     37      - enum:
     38          - sifive,fu540-c000-ccache
     39          - sifive,fu740-c000-ccache
     40      - const: cache
     41
     42  cache-block-size:
     43    const: 64
     44
     45  cache-level:
     46    const: 2
     47
     48  cache-sets:
     49    const: 1024
     50
     51  cache-size:
     52    const: 2097152
     53
     54  cache-unified: true
     55
     56  interrupts:
     57    minItems: 3
     58    items:
     59      - description: DirError interrupt
     60      - description: DataError interrupt
     61      - description: DataFail interrupt
     62      - description: DirFail interrupt
     63
     64  reg:
     65    maxItems: 1
     66
     67  next-level-cache: true
     68
     69  memory-region:
     70    maxItems: 1
     71    description: |
     72      The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
     73      The reserved memory node should be defined as per the bindings in reserved-memory.txt.
     74
     75if:
     76  properties:
     77    compatible:
     78      contains:
     79        const: sifive,fu540-c000-ccache
     80
     81then:
     82  properties:
     83    interrupts:
     84      description: |
     85        Must contain entries for DirError, DataError and DataFail signals.
     86      maxItems: 3
     87
     88else:
     89  properties:
     90    interrupts:
     91      description: |
     92        Must contain entries for DirError, DataError, DataFail, DirFail signals.
     93      minItems: 4
     94
     95additionalProperties: false
     96
     97required:
     98  - compatible
     99  - cache-block-size
    100  - cache-level
    101  - cache-sets
    102  - cache-size
    103  - cache-unified
    104  - interrupts
    105  - reg
    106
    107examples:
    108  - |
    109    cache-controller@2010000 {
    110        compatible = "sifive,fu540-c000-ccache", "cache";
    111        cache-block-size = <64>;
    112        cache-level = <2>;
    113        cache-sets = <1024>;
    114        cache-size = <2097152>;
    115        cache-unified;
    116        reg = <0x2010000 0x1000>;
    117        interrupt-parent = <&plic0>;
    118        interrupts = <1>,
    119                     <2>,
    120                     <3>;
    121        next-level-cache = <&L25>;
    122        memory-region = <&l2_lim>;
    123    };