cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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maxim-ds1302.txt (1115B)


      1* Maxim/Dallas Semiconductor DS-1302 RTC
      2
      3Simple device which could be used to store date/time between reboots.
      4
      5The device uses the standard MicroWire half-duplex transfer timing.
      6Master output is set on low clock and sensed by the RTC on the rising
      7edge. Master input is set by the RTC on the trailing edge and is sensed
      8by the master on low clock.
      9
     10Required properties:
     11
     12- compatible : Should be "maxim,ds1302"
     13
     14Required SPI properties:
     15
     16- reg : Should be address of the device chip select within
     17  the controller.
     18
     19- spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V,
     20  and 2MHz if powered at 5V.
     21
     22- spi-3wire : The device has a shared signal IN/OUT line.
     23
     24- spi-lsb-first : DS-1302 requires least significant bit first
     25  transfers.
     26
     27- spi-cs-high: DS-1302 has active high chip select line. This is
     28  required unless inverted in hardware.
     29
     30Example:
     31
     32spi@901c {
     33	#address-cells = <1>;
     34	#size-cells = <0>;
     35	compatible = "icpdas,lp8841-spi-rtc";
     36	reg = <0x901c 0x1>;
     37
     38	rtc@0 {
     39		compatible = "maxim,ds1302";
     40		reg = <0>;
     41		spi-max-frequency = <500000>;
     42		spi-3wire;
     43		spi-lsb-first;
     44		spi-cs-high;
     45	};
     46};