cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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google,cr50.txt (472B)

      1* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus.
      2
      3H1 Secure Microcontroller running Cr50 firmware provides several
      4functions, including TPM-like functionality. It communicates over
      5SPI using the FIFO protocol described in the PTP Spec, section 6.
      6
      7Required properties:
      8- compatible: Should be "google,cr50".
      9- spi-max-frequency: Maximum SPI frequency.
     10
     11Example:
     12
     13&spi0 {
     14	tpm@0 {
     15		compatible = "google,cr50";
     16		reg = <0>;
     17		spi-max-frequency = <800000>;
     18	};
     19};