cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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st33zp24-spi.txt (952B)

      1* STMicroelectronics SAS. ST33ZP24 TPM SoC
      2
      3Required properties:
      4- compatible: Should be "st,st33zp24-spi".
      5- spi-max-frequency: Maximum SPI frequency (<= 10000000).
      6
      7Optional ST33ZP24 Properties:
      8- interrupts: GPIO interrupt to which the chip is connected
      9- lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state.
     10If set, power must be present when the platform is going into sleep/hibernate mode.
     11
     12Optional SoC Specific Properties:
     13- pinctrl-names: Contains only one value - "default".
     14- pintctrl-0: Specifies the pin control groups used for this controller.
     15
     16Example (for ARM-based BeagleBoard xM with ST33ZP24 on SPI4):
     17
     18&mcspi4 {
     19
     20
     21        st33zp24@0 {
     22
     23                compatible = "st,st33zp24-spi";
     24
     25                spi-max-frequency = <10000000>;
     26
     27                interrupt-parent = <&gpio5>;
     28                interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
     29
     30                lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
     31        };
     32};