cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

amlogic,meson-uart.yaml (2206B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2# Copyright 2019 BayLibre, SAS
      3%YAML 1.2
      4---
      5$id: "http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#"
      6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      7
      8title: Amlogic Meson SoC UART Serial Interface
      9
     10maintainers:
     11  - Neil Armstrong <narmstrong@baylibre.com>
     12
     13description: |
     14  The Amlogic Meson SoC UART Serial Interface is present on a large range
     15  of SoCs, and can be present either in the "Always-On" power domain or the
     16  "Everything-Else" power domain.
     17
     18  The particularity of the "Always-On" Serial Interface is that the hardware
     19  is active since power-on and does not need any clock gating and is usable
     20  as very early serial console.
     21
     22properties:
     23  compatible:
     24    oneOf:
     25      - description: Always-on power domain UART controller
     26        items:
     27          - enum:
     28              - amlogic,meson6-uart
     29              - amlogic,meson8-uart
     30              - amlogic,meson8b-uart
     31              - amlogic,meson-gx-uart
     32              - amlogic,meson-s4-uart
     33          - const: amlogic,meson-ao-uart
     34      - description: Everything-Else power domain UART controller
     35        enum:
     36          - amlogic,meson6-uart
     37          - amlogic,meson8-uart
     38          - amlogic,meson8b-uart
     39          - amlogic,meson-gx-uart
     40          - amlogic,meson-s4-uart
     41
     42  reg:
     43    maxItems: 1
     44
     45  interrupts:
     46    maxItems: 1
     47
     48  clocks:
     49    items:
     50      - description: external xtal clock identifier
     51      - description: the bus core clock, either the clk81 clock or the gate clock
     52      - description: the source of the baudrate generator, can be either the xtal or the pclk
     53
     54  clock-names:
     55    items:
     56      - const: xtal
     57      - const: pclk
     58      - const: baud
     59
     60  fifo-size:
     61    description: The fifo size supported by the UART channel.
     62    $ref: /schemas/types.yaml#/definitions/uint32
     63    enum: [64, 128]
     64
     65required:
     66  - compatible
     67  - reg
     68  - interrupts
     69  - clocks
     70  - clock-names
     71
     72additionalProperties: false
     73
     74examples:
     75  - |
     76    serial@84c0 {
     77          compatible = "amlogic,meson-gx-uart";
     78          reg = <0x84c0 0x14>;
     79          interrupts = <26>;
     80          clocks = <&xtal>, <&pclk>, <&xtal>;
     81          clock-names = "xtal", "pclk", "baud";
     82    };