cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cavium-uart.txt (506B)

      1* Universal Asynchronous Receiver/Transmitter (UART)
      2
      3- compatible: "cavium,octeon-3860-uart"
      4
      5  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
      6
      7- reg: The base address of the UART register bank.
      8
      9- interrupts: A single interrupt specifier.
     10
     11- current-speed: Optional, the current bit rate in bits per second.
     12
     13Example:
     14	uart1: serial@1180000000c00 {
     15		compatible = "cavium,octeon-3860-uart","ns16550";
     16		reg = <0x11800 0x00000c00 0x0 0x400>;
     17		current-speed = <115200>;
     18		interrupts = <0 35>;
     19	};