cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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lantiq_asc.txt (876B)


      1Lantiq SoC ASC serial controller
      2
      3Required properties:
      4- compatible : Should be "lantiq,asc"
      5- reg : Address and length of the register set for the device
      6- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
      7  depends on the interrupt-parent interrupt controller.
      8
      9Optional properties:
     10- clocks: Should contain frequency clock and gate clock
     11- clock-names: Should be "freq" and "asc"
     12
     13Example:
     14
     15asc0: serial@16600000 {
     16	compatible = "lantiq,asc";
     17	reg = <0x16600000 0x100000>;
     18	interrupt-parent = <&gic>;
     19	interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
     20		<GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
     21		<GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
     22	clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
     23	clock-names = "freq", "asc";
     24};
     25
     26asc1: serial@e100c00 {
     27	compatible = "lantiq,asc";
     28	reg = <0xE100C00 0x400>;
     29	interrupt-parent = <&icu0>;
     30	interrupts = <112 113 114>;
     31};