cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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litex,liteuart.yaml (813B)

      1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
      2
      3%YAML 1.2
      4---
      5$id: http://devicetree.org/schemas/serial/litex,liteuart.yaml#
      6$schema: http://devicetree.org/meta-schemas/core.yaml#
      7
      8title: LiteUART serial controller
      9
     10maintainers:
     11  - Karol Gugala <kgugala@antmicro.com>
     12  - Mateusz Holenko <mholenko@antmicro.com>
     13
     14description: |
     15  LiteUART serial controller is a part of the LiteX FPGA SoC builder. It supports
     16  multiple CPU architectures, currently including e.g. OpenRISC and RISC-V.
     17
     18properties:
     19  compatible:
     20    const: litex,liteuart
     21
     22  reg:
     23    maxItems: 1
     24
     25  interrupts:
     26    maxItems: 1
     27
     28required:
     29  - compatible
     30  - reg
     31
     32additionalProperties: false
     33
     34examples:
     35  - |
     36    uart0: serial@e0001800 {
     37      compatible = "litex,liteuart";
     38      reg = <0xe0001800 0x100>;
     39      interrupts = <2>;
     40    };