cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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maxim,max310x.txt (1306B)


      1* Maxim MAX310X advanced Universal Asynchronous Receiver-Transmitter (UART)
      2
      3Required properties:
      4- compatible: Should be one of the following:
      5  - "maxim,max3107" for Maxim MAX3107,
      6  - "maxim,max3108" for Maxim MAX3108,
      7  - "maxim,max3109" for Maxim MAX3109,
      8  - "maxim,max14830" for Maxim MAX14830.
      9- reg: SPI chip select number.
     10- interrupts: Specifies the interrupt source of the parent interrupt
     11  controller. The format of the interrupt specifier depends on the
     12  parent interrupt controller.
     13- clocks: phandle to the IC source clock.
     14- clock-names: Should be "xtal" if clock is an external crystal or
     15  "osc" if an external clock source is used.
     16
     17Optional properties:
     18- gpio-controller: Marks the device node as a GPIO controller.
     19- #gpio-cells: Should be two. The first cell is the GPIO number and
     20  the second cell is used to specify the GPIO polarity:
     21    0 = active high,
     22    1 = active low.
     23
     24Example:
     25
     26/ {
     27	clocks {
     28		spi_uart_clk: osc_max14830 {
     29			compatible = "fixed-clock";
     30			#clock-cells = <0>;
     31			clock-frequency = <3686400>;
     32		};
     33
     34	};
     35};
     36
     37&spi0 {
     38	max14830: max14830@0 {
     39		compatible = "maxim,max14830";
     40		reg = <0>;
     41		clocks = <&spi_uart_clk>;
     42		clock-names = "osc";
     43		interrupt-parent = <&gpio3>;
     44		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
     45		gpio-controller;
     46		#gpio-cells = <2>;
     47	};
     48};