cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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microchip,pic32-uart.txt (985B)

      1* Microchip Universal Asynchronous Receiver Transmitter (UART)
      2
      3Required properties:
      4- compatible: Should be "microchip,pic32mzda-uart"
      5- reg: Should contain registers location and length
      6- interrupts: Should contain interrupt
      7- clocks: Phandle to the clock.
      8          See: Documentation/devicetree/bindings/clock/clock-bindings.txt
      9- pinctrl-names: A pinctrl state names "default" must be defined.
     10- pinctrl-0: Phandle referencing pin configuration of the UART peripheral.
     11             See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
     12
     13Optional properties:
     14- cts-gpios: CTS pin for UART
     15
     16Example:
     17	uart1: serial@1f822000 {
     18		compatible = "microchip,pic32mzda-uart";
     19		reg = <0x1f822000 0x50>;
     20		interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
     21			<113 IRQ_TYPE_LEVEL_HIGH>,
     22			<114 IRQ_TYPE_LEVEL_HIGH>;
     23		clocks = <&rootclk PB2CLK>;
     24		pinctrl-names = "default";
     25		pinctrl-0 = <&pinctrl_uart1
     26				&pinctrl_uart1_cts
     27				&pinctrl_uart1_rts>;
     28		cts-gpios = <&gpio1 15 0>;
     29	};