cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nvidia,tegra20-hsuart.txt (3003B)


      1NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
      2
      3Required properties:
      4- compatible : should be,
      5  "nvidia,tegra20-hsuart" for Tegra20,
      6  "nvidia,tegra30-hsuart" for Tegra30,
      7  "nvidia,tegra186-hsuart" for Tegra186,
      8  "nvidia,tegra194-hsuart" for Tegra194.
      9
     10- reg: Should contain UART controller registers location and length.
     11- interrupts: Should contain UART controller interrupts.
     12- clocks: Must contain one entry, for the module clock.
     13  See ../clocks/clock-bindings.txt for details.
     14- resets : Must contain an entry for each entry in reset-names.
     15  See ../reset/reset.txt for details.
     16- reset-names : Must include the following entries:
     17  - serial
     18- dmas : Must contain an entry for each entry in dma-names.
     19  See ../dma/dma.txt for details.
     20- dma-names : Must include the following entries:
     21  - rx
     22  - tx
     23
     24Optional properties:
     25- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
     26		only if all 8 lines of UART controller are pinmuxed.
     27- nvidia,adjust-baud-rates: List of entries providing percentage of baud rate
     28  adjustment within a range.
     29  Each entry contains sets of 3 values. Range low/high and adjusted rate.
     30  <range_low range_high adjusted_rate>
     31  When baud rate set on controller falls within the range mentioned in this
     32  field, baud rate will be adjusted by percentage mentioned here.
     33  Ex: <9600 115200 200>
     34  Increase baud rate by 2% when set baud rate falls within range 9600 to 115200
     35
     36Baud Rate tolerance:
     37  Standard UART devices are expected to have tolerance for baud rate error by
     38  -4 to +4 %. All Tegra devices till Tegra210 had this support. However,
     39  Tegra186 chip has a known hardware issue. UART Rx baud rate tolerance level
     40  is 0% to +4% in 1-stop config. Otherwise, the received data will have
     41  corruption/invalid framing errors. Parker errata suggests adjusting baud
     42  rate to be higher than the deviations observed in Tx.
     43
     44  Tx deviation of connected device can be captured over scope (or noted from
     45  its spec) for valid range and Tegra baud rate has to be set above actual
     46  Tx baud rate observed. To do this we use nvidia,adjust-baud-rates
     47
     48  As an example, consider there is deviation observed in Tx for baud rates as
     49  listed below.
     50  0 to 9600 has 1% deviation
     51  9600 to 115200 2% deviation
     52  This slight deviation is expcted and Tegra UART is expected to handle it. Due
     53  to the issue stated above, baud rate on Tegra UART should be set equal to or
     54  above deviation observed for avoiding frame errors.
     55  Property should be set like this
     56  nvidia,adjust-baud-rates = <0 9600 100>,
     57  			     <9600 115200 200>;
     58
     59Example:
     60
     61serial@70006000 {
     62	compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart";
     63	reg = <0x70006000 0x40>;
     64	reg-shift = <2>;
     65	interrupts = <0 36 0x04>;
     66	nvidia,enable-modem-interrupt;
     67	clocks = <&tegra_car 6>;
     68	resets = <&tegra_car 6>;
     69	reset-names = "serial";
     70	dmas = <&apbdma 8>, <&apbdma 8>;
     71	dma-names = "rx", "tx";
     72	nvidia,adjust-baud-rates = <1000000 4000000 136>; /* 1.36% shift */
     73};