cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pl011.yaml (2436B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/serial/pl011.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: ARM AMBA Primecell PL011 serial UART
      8
      9maintainers:
     10  - Rob Herring <robh@kernel.org>
     11
     12allOf:
     13  - $ref: serial.yaml#
     14
     15# Need a custom select here or 'arm,primecell' will match on lots of nodes
     16select:
     17  properties:
     18    compatible:
     19      contains:
     20        enum:
     21          - arm,pl011
     22  required:
     23    - compatible
     24
     25properties:
     26  compatible:
     27    items:
     28      - const: arm,pl011
     29      - const: arm,primecell
     30
     31  reg:
     32    maxItems: 1
     33
     34  interrupts:
     35    maxItems: 1
     36
     37  pinctrl-0: true
     38  pinctrl-1: true
     39
     40  pinctrl-names:
     41    description:
     42      When present, must have one state named "default",
     43      and may contain a second name named "sleep". The former
     44      state sets up pins for ordinary operation whereas
     45      the latter state will put the associated pins to sleep
     46      when the UART is unused
     47    minItems: 1
     48    items:
     49      - const: default
     50      - const: sleep
     51
     52  clocks:
     53    description:
     54      When present, the first clock listed must correspond to
     55      the clock named UARTCLK on the IP block, i.e. the clock
     56      to the external serial line, whereas the second clock
     57      must correspond to the PCLK clocking the internal logic
     58      of the block. Just listing one clock (the first one) is
     59      deprecated.
     60    maxItems: 2
     61
     62  clock-names:
     63    items:
     64      - const: uartclk
     65      - const: apb_pclk
     66
     67  dmas:
     68    minItems: 1
     69    maxItems: 2
     70
     71  dma-names:
     72    minItems: 1
     73    items:
     74      - const: rx
     75      - const: tx
     76
     77  auto-poll:
     78    description:
     79      Enables polling when using RX DMA.
     80    type: boolean
     81
     82  poll-rate-ms:
     83    description:
     84      Rate at which poll occurs when auto-poll is set.
     85      default 100ms.
     86    default: 100
     87
     88  poll-timeout-ms:
     89    description:
     90      Poll timeout when auto-poll is set, default
     91      3000ms.
     92    default: 3000
     93
     94  resets:
     95    maxItems: 1
     96
     97required:
     98  - compatible
     99  - reg
    100  - interrupts
    101
    102dependencies:
    103  poll-rate-ms: [ auto-poll ]
    104  poll-timeout-ms: [ auto-poll ]
    105
    106unevaluatedProperties: false
    107
    108examples:
    109  - |
    110    serial@80120000 {
    111      compatible = "arm,pl011", "arm,primecell";
    112      reg = <0x80120000 0x1000>;
    113      interrupts = <0 11 4>;
    114      dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>;
    115      dma-names = "rx", "tx";
    116      clocks = <&foo_clk>, <&bar_clk>;
    117      clock-names = "uartclk", "apb_pclk";
    118    };
    119
    120...