cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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vt8500-uart.txt (711B)

      1* VIA VT8500 and WonderMedia WM8xxx UART Controller
      2
      3Required properties:
      4- compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and
      5	including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later)
      6
      7- reg: base physical address of the controller and length of memory mapped
      8	region.
      9
     10- interrupts: hardware interrupt number
     11
     12- clocks: shall be the input parent clock phandle for the clock. This should
     13	be the 24Mhz reference clock.
     14
     15Aliases may be defined to ensure the correct ordering of the uarts.
     16
     17Example:
     18	aliases {
     19		serial0 = &uart0;
     20	};
     21
     22	uart0: serial@d8200000 {
     23		compatible = "via,vt8500-uart";
     24		reg = <0xd8200000 0x1040>;
     25		interrupts = <32>;
     26		clocks = <&clkuart0>;
     27	};