cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

pincfg.txt (1828B)


      1* Pin configuration nodes
      2
      3Required properties:
      4- pio-map : array of pin configurations.  Each pin is defined by 6
      5  integers.  The six numbers are respectively: port, pin, dir,
      6  open_drain, assignment, has_irq.
      7  - port : port number of the pin; 0-6 represent port A-G in UM.
      8  - pin : pin number in the port.
      9  - dir : direction of the pin, should encode as follows:
     10
     11     0 = The pin is disabled
     12     1 = The pin is an output
     13     2 = The pin is an input
     14     3 = The pin is I/O
     15
     16  - open_drain : indicates the pin is normal or wired-OR:
     17
     18     0 = The pin is actively driven as an output
     19     1 = The pin is an open-drain driver. As an output, the pin is
     20         driven active-low, otherwise it is three-stated.
     21
     22  - assignment : function number of the pin according to the Pin Assignment
     23    tables in User Manual.  Each pin can have up to 4 possible functions in
     24    QE and two options for CPM.
     25  - has_irq : indicates if the pin is used as source of external
     26    interrupts.
     27
     28Example:
     29     ucc_pin@1 {
     30	pio-map = <
     31	/* port  pin  dir  open_drain  assignment  has_irq */
     32		0  3  1  0  1  0 	/* TxD0 */
     33		0  4  1  0  1  0 	/* TxD1 */
     34		0  5  1  0  1  0 	/* TxD2 */
     35		0  6  1  0  1  0 	/* TxD3 */
     36		1  6  1  0  3  0 	/* TxD4 */
     37		1  7  1  0  1  0 	/* TxD5 */
     38		1  9  1  0  2  0 	/* TxD6 */
     39		1  a  1  0  2  0 	/* TxD7 */
     40		0  9  2  0  1  0 	/* RxD0 */
     41		0  a  2  0  1  0 	/* RxD1 */
     42		0  b  2  0  1  0 	/* RxD2 */
     43		0  c  2  0  1  0 	/* RxD3 */
     44		0  d  2  0  1  0 	/* RxD4 */
     45		1  1  2  0  2  0 	/* RxD5 */
     46		1  0  2  0  2  0 	/* RxD6 */
     47		1  4  2  0  2  0 	/* RxD7 */
     48		0  7  1  0  1  0 	/* TX_EN */
     49		0  8  1  0  1  0 	/* TX_ER */
     50		0  f  2  0  1  0 	/* RX_DV */
     51		0  10 2  0  1  0 	/* RX_ER */
     52		0  0  2  0  1  0 	/* RX_CLK */
     53		2  9  1  0  3  0 	/* GTX_CLK - CLK10 */
     54		2  8  2  0  1  0>;	/* GTX125 - CLK9 */
     55     };
     56
     57